mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-10-31 03:32:29 +00:00
Code Activity

Trim A_WIDTH by Y_WIDTH-1

Browse source
This commit is contained in:
Eddie Hung 2019-04-22 17:14:11 -07:00
parent 69863f7698
commit 1fa2c36fbd
1 changed files with 1 additions and 1 deletions
Download patch file Download diff file Expand all files Collapse all files

2
techlibs/xilinx/cells_map.v
View file

@ -168,7 +168,7 @@ module \$shiftx (A, B, Y);
end
else if (Y_WIDTH > 1) begin
for (i = 0; i < Y_WIDTH; i++)
\$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH), .B_WIDTH(B_WIDTH), .Y_WIDTH(1'd1)) bitblast (.A({{i{1'bx}}, A[A_WIDTH-1:i]}), .B(B), .Y(Y[i]));
\$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH-Y_WIDTH+1), .B_WIDTH(B_WIDTH), .Y_WIDTH(1'd1)) bitblast (.A(A[A_WIDTH-Y_WIDTH+i:i]), .B(B), .Y(Y[i]));
end
// If the LSB of B is constant zero (and Y_WIDTH is 1) then
// we can optimise by removing every other entry from A