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Remove BUFGCTRL, BUFHCE and LUT6_2 from cells_xtra.

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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
This commit is contained in:
Keith Rothman 2019-04-12 09:30:49 -07:00
parent e107ccdde8
commit 1f9235ede5
3 changed files with 14 additions and 52 deletions
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22
techlibs/xilinx/cells_sim.v
View file

@ -53,15 +53,15 @@ module BUFGCTRL(
input CE0, input CE1, input CE0, input CE1,
input IGNORE0, input IGNORE1); input IGNORE0, input IGNORE1);
parameter INIT_OUT = 0; parameter [0:0] INIT_OUT = 1'b0;
parameter PRESELECT_I0 = 0; parameter PRESELECT_I0 = "FALSE";
parameter PRESELECT_I1 = 0; parameter PRESELECT_I1 = "FALSE";
parameter IS_CE0_INVERTED = 0; parameter [0:0] IS_CE0_INVERTED = 1'b0;
parameter IS_CE1_INVERTED = 0; parameter [0:0] IS_CE1_INVERTED = 1'b0;
parameter IS_S0_INVERTED = 0; parameter [0:0] IS_S0_INVERTED = 1'b0;
parameter IS_S1_INVERTED = 0; parameter [0:0] IS_S1_INVERTED = 1'b0;
parameter IS_IGNORE0_INVERTED = 0; parameter [0:0] IS_IGNORE0_INVERTED = 1'b0;
parameter IS_IGNORE1_INVERTED = 0; parameter [0:0] IS_IGNORE1_INVERTED = 1'b0;
wire I0_internal = ((CE0 ^ IS_CE0_INVERTED) ? I0 : INIT_OUT); wire I0_internal = ((CE0 ^ IS_CE0_INVERTED) ? I0 : INIT_OUT);
wire I1_internal = ((CE1 ^ IS_CE1_INVERTED) ? I1 : INIT_OUT); wire I1_internal = ((CE1 ^ IS_CE1_INVERTED) ? I1 : INIT_OUT);
@ -74,9 +74,9 @@ endmodule
module BUFHCE(output O, input I, input CE); module BUFHCE(output O, input I, input CE);
parameter INIT_OUT = 0; parameter [0:0] INIT_OUT = 1'b0;
parameter CE_TYPE = "SYNC"; parameter CE_TYPE = "SYNC";
parameter IS_CE_INVERTED = 0; parameter [0:0] IS_CE_INVERTED = 1'b0;
assign O = ((CE ^ IS_CE_INVERTED) ? I : INIT_OUT); assign O = ((CE ^ IS_CE_INVERTED) ? I : INIT_OUT);

6
techlibs/xilinx/cells_xtra.sh
View file

@ -28,12 +28,12 @@ function xtract_cell_decl()
# xtract_cell_decl BUFG # xtract_cell_decl BUFG
xtract_cell_decl BUFGCE xtract_cell_decl BUFGCE
xtract_cell_decl BUFGCE_1 xtract_cell_decl BUFGCE_1
xtract_cell_decl BUFGCTRL #xtract_cell_decl BUFGCTRL
xtract_cell_decl BUFGMUX xtract_cell_decl BUFGMUX
xtract_cell_decl BUFGMUX_1 xtract_cell_decl BUFGMUX_1
xtract_cell_decl BUFGMUX_CTRL xtract_cell_decl BUFGMUX_CTRL
xtract_cell_decl BUFH xtract_cell_decl BUFH
xtract_cell_decl BUFHCE #xtract_cell_decl BUFHCE
xtract_cell_decl BUFIO xtract_cell_decl BUFIO
xtract_cell_decl BUFMR xtract_cell_decl BUFMR
xtract_cell_decl BUFMRCE xtract_cell_decl BUFMRCE
@ -92,7 +92,7 @@ function xtract_cell_decl()
# xtract_cell_decl LUT4 # xtract_cell_decl LUT4
# xtract_cell_decl LUT5 # xtract_cell_decl LUT5
# xtract_cell_decl LUT6 # xtract_cell_decl LUT6
xtract_cell_decl LUT6_2 #xtract_cell_decl LUT6_2
xtract_cell_decl MMCME2_ADV xtract_cell_decl MMCME2_ADV
xtract_cell_decl MMCME2_BASE xtract_cell_decl MMCME2_BASE
# xtract_cell_decl MUXF7 # xtract_cell_decl MUXF7

38
techlibs/xilinx/cells_xtra.v
View file

@ -30,29 +30,6 @@ module BUFGCE_1 (...);
input CE, I; input CE, I;
endmodule endmodule
module BUFGCTRL (...);
output O;
input CE0;
input CE1;
input I0;
input I1;
input IGNORE0;
input IGNORE1;
input S0;
input S1;
parameter integer INIT_OUT = 0;
parameter PRESELECT_I0 = "FALSE";
parameter PRESELECT_I1 = "FALSE";
parameter [0:0] IS_CE0_INVERTED = 1'b0;
parameter [0:0] IS_CE1_INVERTED = 1'b0;
parameter [0:0] IS_I0_INVERTED = 1'b0;
parameter [0:0] IS_I1_INVERTED = 1'b0;
parameter [0:0] IS_IGNORE0_INVERTED = 1'b0;
parameter [0:0] IS_IGNORE1_INVERTED = 1'b0;
parameter [0:0] IS_S0_INVERTED = 1'b0;
parameter [0:0] IS_S1_INVERTED = 1'b0;
endmodule
module BUFGMUX (...); module BUFGMUX (...);
parameter CLK_SEL_TYPE = "SYNC"; parameter CLK_SEL_TYPE = "SYNC";
output O; output O;
@ -77,15 +54,6 @@ module BUFH (...);
input I; input I;
endmodule endmodule
module BUFHCE (...);
parameter CE_TYPE = "SYNC";
parameter integer INIT_OUT = 0;
parameter [0:0] IS_CE_INVERTED = 1'b0;
output O;
input CE;
input I;
endmodule
module BUFIO (...); module BUFIO (...);
output O; output O;
input I; input I;
@ -2420,12 +2388,6 @@ module LDPE (...);
input D, G, GE, PRE; input D, G, GE, PRE;
endmodule endmodule
module LUT6_2 (...);
parameter [63:0] INIT = 64'h0000000000000000;
input I0, I1, I2, I3, I4, I5;
output O5, O6;
endmodule
module MMCME2_ADV (...); module MMCME2_ADV (...);
parameter BANDWIDTH = "OPTIMIZED"; parameter BANDWIDTH = "OPTIMIZED";
parameter real CLKFBOUT_MULT_F = 5.000; parameter real CLKFBOUT_MULT_F = 5.000;