mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-08-17 16:52:16 +00:00
Code Activity

Remove BUFGCTRL, BUFHCE and LUT6_2 from cells_xtra.

Browse source 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
This commit is contained in:
Keith Rothman 2019-04-12 09:30:49 -07:00
parent e107ccdde8
commit 1f9235ede5
3 changed files with 14 additions and 52 deletions
Download patch file Download diff file Expand all files Collapse all files

22
techlibs/xilinx/cells_sim.v
View file

@ -53,15 +53,15 @@ module BUFGCTRL(
input CE0, input CE1,
input IGNORE0, input IGNORE1);
parameter INIT_OUT = 0;
parameter PRESELECT_I0 = 0;
parameter PRESELECT_I1 = 0;
parameter IS_CE0_INVERTED = 0;
parameter IS_CE1_INVERTED = 0;
parameter IS_S0_INVERTED = 0;
parameter IS_S1_INVERTED = 0;
parameter IS_IGNORE0_INVERTED = 0;
parameter IS_IGNORE1_INVERTED = 0;
parameter [0:0] INIT_OUT = 1'b0;
parameter PRESELECT_I0 = "FALSE";
parameter PRESELECT_I1 = "FALSE";
parameter [0:0] IS_CE0_INVERTED = 1'b0;
parameter [0:0] IS_CE1_INVERTED = 1'b0;
parameter [0:0] IS_S0_INVERTED = 1'b0;
parameter [0:0] IS_S1_INVERTED = 1'b0;
parameter [0:0] IS_IGNORE0_INVERTED = 1'b0;
parameter [0:0] IS_IGNORE1_INVERTED = 1'b0;
wire I0_internal = ((CE0 ^ IS_CE0_INVERTED) ? I0 : INIT_OUT);
wire I1_internal = ((CE1 ^ IS_CE1_INVERTED) ? I1 : INIT_OUT);
@ -74,9 +74,9 @@ endmodule
module BUFHCE(output O, input I, input CE);
parameter INIT_OUT = 0;
parameter [0:0] INIT_OUT = 1'b0;
parameter CE_TYPE = "SYNC";
parameter IS_CE_INVERTED = 0;
parameter [0:0] IS_CE_INVERTED = 1'b0;
assign O = ((CE ^ IS_CE_INVERTED) ? I : INIT_OUT);