From 672c89498a1e21065b2d3624cb705134656783e5 Mon Sep 17 00:00:00 2001 From: Zapta Date: Sat, 2 Mar 2024 11:20:53 -0800 Subject: [PATCH 1/3] Added to the Show command a -wireshape flag. This allows to control the shape of wire nodes, for example, -wireshape plaintext. The motivation is to allow the user to reduce visual loads of wires. This does not change the default behavior of using a diamond shape. --- passes/cmds/show.cc | 26 +++++++++++++++++++------- 1 file changed, 19 insertions(+), 7 deletions(-) diff --git a/passes/cmds/show.cc b/passes/cmds/show.cc index 82b5c6bcf..9383aafcd 100644 --- a/passes/cmds/show.cc +++ b/passes/cmds/show.cc @@ -60,6 +60,7 @@ struct ShowWorker RTLIL::Module *module; uint32_t currentColor; bool genWidthLabels; + std::string wireshape; bool genSignedLabels; bool stretchIO; bool enumerateIds; @@ -429,16 +430,19 @@ struct ShowWorker std::map wires_on_demand; for (auto wire : module->selected_wires()) { - const char *shape = "diamond"; + std::string shape = wireshape; if (wire->port_input || wire->port_output) shape = "octagon"; + const bool is_borderless = (shape == "plaintext") || (shape == "plain") || (shape == "none"); if (wire->name.isPublic()) { std::string src_href; if (href && wire->attributes.count(ID::src) > 0) src_href = stringf(", href=\"%s\" ", escape(wire->attributes.at(ID::src).decode_string())); - fprintf(f, "n%d [ shape=%s, label=\"%s\", %s%s];\n", - id2num(wire->name), shape, findLabel(wire->name.str()), - nextColor(RTLIL::SigSpec(wire), "color=\"black\", fontcolor=\"black\"").c_str(), + fprintf(f, "n%d [ shape=%s,%s label=\"%s\", %s%s];\n", + id2num(wire->name), shape.c_str(), is_borderless? " margin=0, width=0" : "", findLabel(wire->name.str()), + is_borderless + ? "color=\"none\", fontcolor=\"black\"" + : nextColor(RTLIL::SigSpec(wire), "color=\"black\", fontcolor=\"black\"").c_str(), src_href.c_str()); if (wire->port_input) all_sources.insert(stringf("n%d", id2num(wire->name))); @@ -617,10 +621,10 @@ struct ShowWorker } ShowWorker(FILE *f, RTLIL::Design *design, std::vector &libs, uint32_t colorSeed, bool genWidthLabels, - bool genSignedLabels, bool stretchIO, bool enumerateIds, bool abbreviateIds, bool notitle, bool href, + const std::string wireshape, bool genSignedLabels, bool stretchIO, bool enumerateIds, bool abbreviateIds, bool notitle, bool href, const std::vector> &color_selections, const std::vector> &label_selections, RTLIL::IdString colorattr) : - f(f), design(design), currentColor(colorSeed), genWidthLabels(genWidthLabels), + f(f), design(design), currentColor(colorSeed), genWidthLabels(genWidthLabels), wireshape(wireshape), genSignedLabels(genSignedLabels), stretchIO(stretchIO), enumerateIds(enumerateIds), abbreviateIds(abbreviateIds), notitle(notitle), href(href), color_selections(color_selections), label_selections(label_selections), colorattr(colorattr) { @@ -708,6 +712,9 @@ struct ShowPass : public Pass { log(" Use the specified attribute to assign colors. A unique color is\n"); log(" assigned to each unique value of this attribute.\n"); log("\n"); + log(" -wireshape \n"); + log(" Use the specified shape for wire nodes. E.g. plaintext.\n"); + log("\n"); log(" -width\n"); log(" annotate buses with a label indicating the width of the bus.\n"); log("\n"); @@ -766,6 +773,7 @@ struct ShowPass : public Pass { std::string prefix = stringf("%s/.yosys_show", getenv("HOME") ? getenv("HOME") : "."); #endif std::string viewer_exe; + std::string flag_wireshape = "diamond"; std::vector libfiles; std::vector libs; uint32_t colorSeed = 0; @@ -830,6 +838,10 @@ struct ShowPass : public Pass { format = args[++argidx]; continue; } + if (arg == "-wireshape" && argidx+1 < args.size()) { + flag_wireshape = args[++argidx]; + continue; + } if (arg == "-width") { flag_width= true; continue; @@ -912,7 +924,7 @@ struct ShowPass : public Pass { delete lib; log_cmd_error("Can't open dot file `%s' for writing.\n", dot_file.c_str()); } - ShowWorker worker(f, design, libs, colorSeed, flag_width, flag_signed, flag_stretch, flag_enum, flag_abbreviate, flag_notitle, flag_href, color_selections, label_selections, colorattr); + ShowWorker worker(f, design, libs, colorSeed, flag_width, flag_wireshape, flag_signed, flag_stretch, flag_enum, flag_abbreviate, flag_notitle, flag_href, color_selections, label_selections, colorattr); fclose(f); for (auto lib : libs) From bc24947a849e9e5068c04cc663eb3379c0995523 Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Thu, 11 Sep 2025 16:50:23 +0200 Subject: [PATCH 2/3] tests: replace CC and gcc with CXX and g++ --- tests/cxxrtl/run-test.sh | 4 ++-- tests/fmt/run-test.sh | 4 ++-- tests/tools/autotest.sh | 2 +- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/tests/cxxrtl/run-test.sh b/tests/cxxrtl/run-test.sh index ee299fc82..4b542e180 100755 --- a/tests/cxxrtl/run-test.sh +++ b/tests/cxxrtl/run-test.sh @@ -5,7 +5,7 @@ set -ex run_subtest () { local subtest=$1; shift - ${CC:-gcc} -std=c++11 -O2 -o cxxrtl-test-${subtest} -I../../backends/cxxrtl/runtime test_${subtest}.cc -lstdc++ + ${CXX:-g++} -std=c++11 -O2 -o cxxrtl-test-${subtest} -I../../backends/cxxrtl/runtime test_${subtest}.cc -lstdc++ ./cxxrtl-test-${subtest} } @@ -14,4 +14,4 @@ run_subtest value_fuzz # Compile-only test. ../../yosys -p "read_verilog test_unconnected_output.v; select =*; proc; clean; write_cxxrtl cxxrtl-test-unconnected_output.cc" -${CC:-gcc} -std=c++11 -c -o cxxrtl-test-unconnected_output -I../../backends/cxxrtl/runtime cxxrtl-test-unconnected_output.cc +${CXX:-g++} -std=c++11 -c -o cxxrtl-test-unconnected_output -I../../backends/cxxrtl/runtime cxxrtl-test-unconnected_output.cc diff --git a/tests/fmt/run-test.sh b/tests/fmt/run-test.sh index 998047f83..88ee6e238 100644 --- a/tests/fmt/run-test.sh +++ b/tests/fmt/run-test.sh @@ -51,7 +51,7 @@ test_cxxrtl () { local subtest=$1; shift ../../yosys -p "read_verilog ${subtest}.v; proc; clean; write_cxxrtl -print-output std::cerr yosys-${subtest}.cc" - ${CC:-gcc} -std=c++11 -o yosys-${subtest} -I../../backends/cxxrtl/runtime ${subtest}_tb.cc -lstdc++ + ${CXX:-g++} -std=c++11 -o yosys-${subtest} -I../../backends/cxxrtl/runtime ${subtest}_tb.cc -lstdc++ ./yosys-${subtest} 2>yosys-${subtest}.log iverilog -o iverilog-${subtest} ${subtest}.v ${subtest}_tb.v ./iverilog-${subtest} |grep -v '\$finish called' >iverilog-${subtest}.log @@ -69,7 +69,7 @@ diff iverilog-always_full.log iverilog-always_full-1.log ../../yosys -p "read_verilog display_lm.v" >yosys-display_lm.log ../../yosys -p "read_verilog display_lm.v; write_cxxrtl yosys-display_lm.cc" -${CC:-gcc} -std=c++11 -o yosys-display_lm_cc -I../../backends/cxxrtl/runtime display_lm_tb.cc -lstdc++ +${CXX:-g++} -std=c++11 -o yosys-display_lm_cc -I../../backends/cxxrtl/runtime display_lm_tb.cc -lstdc++ ./yosys-display_lm_cc >yosys-display_lm_cc.log for log in yosys-display_lm.log yosys-display_lm_cc.log; do grep "^%l: \\\\bot\$" "$log" diff --git a/tests/tools/autotest.sh b/tests/tools/autotest.sh index f96eb8d71..47b06d575 100755 --- a/tests/tools/autotest.sh +++ b/tests/tools/autotest.sh @@ -26,7 +26,7 @@ xfirrtl="../xfirrtl" abcprog="$toolsdir/../../yosys-abc" if [ ! -f "$toolsdir/cmp_tbdata" -o "$toolsdir/cmp_tbdata.c" -nt "$toolsdir/cmp_tbdata" ]; then - ( set -ex; ${CC:-gcc} -Wall -o "$toolsdir/cmp_tbdata" "$toolsdir/cmp_tbdata.c"; ) || exit 1 + ( set -ex; ${CXX:-g++} -Wall -o "$toolsdir/cmp_tbdata" "$toolsdir/cmp_tbdata.c"; ) || exit 1 fi while getopts xmGl:wkjvref:s:p:n:S:I:A:-: opt; do From 3d2bb1db17e119efbf58134acc089c2b5867a451 Mon Sep 17 00:00:00 2001 From: Xing Guo Date: Sat, 13 Sep 2025 11:19:29 +0800 Subject: [PATCH 3/3] verilog_parser: replace manual AST node allocation with typed midrule actions Use Bison's typed midrule actions to construct AST_FCALL nodes with std::unique_ptr, replacing manual 'new' and extra->ast_stack management. This improves type safety, ensures proper ownership, and eliminates potential memory leaks. Ref: https://www.gnu.org/software/bison/manual/html_node/Typed-Midrule-Actions.html --- frontends/verilog/verilog_parser.y | 20 ++++++++++++-------- 1 file changed, 12 insertions(+), 8 deletions(-) diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index d8b0088b9..ef8427679 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -3289,15 +3289,19 @@ basic_expr: $$ = AstNode::mkconst_str(@1, *$1); SET_AST_NODE_LOC($$.get(), @1, @1); } | - hierarchical_id attr { - // super sketchy! Orphaned pointer in non-owning extra->ast_stack - AstNode *node = new AstNode(@1, AST_FCALL); - node->str = *$1; - extra->ast_stack.push_back(node); - SET_AST_NODE_LOC(node, @1, @1); - append_attr(node, std::move($2)); + hierarchical_id attr { + // Here we use "Typed Midrule Actions". + // https://www.gnu.org/software/bison/manual/html_node/Typed-Midrule-Actions.html + auto fcall = std::make_unique(@1, AST_FCALL); + AstNode *fcall_node = fcall.get(); + fcall_node->str = *$1; + extra->ast_stack.push_back(fcall_node); + SET_AST_NODE_LOC(fcall_node, @1, @1); + append_attr(fcall_node, std::move($2)); + $$ = std::move(fcall); } TOK_LPAREN arg_list optional_comma TOK_RPAREN { - $$.reset(extra->ast_stack.back()); + log_assert($3 != nullptr); + $$ = std::move($3); extra->ast_stack.pop_back(); } | TOK_TO_SIGNED attr TOK_LPAREN expr TOK_RPAREN {