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memory_share: Add -nosat and -nowiden options.

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This unlocks wide port recognition by default.
This commit is contained in:
Marcelina Kościelnicka 2021-05-29 17:45:05 +02:00
parent 9fdedf4d1c
commit 1f74ec3535
11 changed files with 269 additions and 11 deletions
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8
tests/memories/run-test.sh
View file

@ -23,6 +23,10 @@ for f in `egrep -l 'expect-(wr-ports|rd-ports|rd-clk)' *.v`; do
grep -q "parameter \\\\WR_PORTS $(gawk '/expect-wr-ports/ { print $3; }' $f)\$" ${f%.v}.dmp ||
{ echo " ERROR: Unexpected number of write ports."; false; }
fi
if grep -q expect-wr-wide-continuation $f; then
grep -q "parameter \\\\WR_WIDE_CONTINUATION $(gawk '/expect-wr-wide-continuation/ { print $3; }' $f)\$" ${f%.v}.dmp ||
{ echo " ERROR: Unexpected write wide continuation."; false; }
fi
if grep -q expect-rd-ports $f; then
grep -q "parameter \\\\RD_PORTS $(gawk '/expect-rd-ports/ { print $3; }' $f)\$" ${f%.v}.dmp ||
{ echo " ERROR: Unexpected number of read ports."; false; }
@ -55,6 +59,10 @@ for f in `egrep -l 'expect-(wr-ports|rd-ports|rd-clk)' *.v`; do
grep -q "parameter \\\\RD_INIT_VALUE $(gawk '/expect-rd-init-val/ { print $3; }' $f)\$" ${f%.v}.dmp ||
{ echo " ERROR: Unexpected read init value."; false; }
fi
if grep -q expect-rd-wide-continuation $f; then
grep -q "parameter \\\\RD_WIDE_CONTINUATION $(gawk '/expect-rd-wide-continuation/ { print $3; }' $f)\$" ${f%.v}.dmp ||
{ echo " ERROR: Unexpected read wide continuation."; false; }
fi
if grep -q expect-no-rd-clk $f; then
grep -q "connect \\\\RD_CLK 1'x\$" ${f%.v}.dmp ||
{ echo " ERROR: Expected no read clock."; false; }

27
tests/memories/wide_read_async.v Normal file
View file

@ -0,0 +1,27 @@
// expect-wr-ports 1
// expect-rd-ports 4
// expect-rd-wide-continuation 4'1110
module test(
input clk,
input we,
input [5:0] ra,
input [7:0] wa,
input [7:0] wd,
output [31:0] rd
);
reg [7:0] mem[0:255];
assign rd[7:0] = mem[{ra, 2'b00}];
assign rd[15:8] = mem[{ra, 2'b01}];
assign rd[23:16] = mem[{ra, 2'b10}];
assign rd[31:24] = mem[{ra, 2'b11}];
always @(posedge clk) begin
if (we)
mem[wa] <= wd;
end
endmodule

46
tests/memories/wide_read_mixed.v Normal file
View file

@ -0,0 +1,46 @@
// expect-wr-ports 1
// expect-rd-ports 4
// expect-rd-wide-continuation 4'1110
// expect-rd-srst-val 32'10000111011001010100001100100001
// expect-rd-init-val 32'10101011110011011110111110101011
// In this testcase, the byte-wide read ports are merged into a single
// word-wide port despite mismatched transparency, with soft transparency
// logic inserted on half the port to preserve the semantics.
module test(
input clk,
input re, rr,
input we,
input [5:0] ra,
input [7:0] wa,
input [7:0] wd,
output reg [31:0] rd
);
reg [7:0] mem[0:255];
initial rd = 32'habcdefab;
always @(posedge clk) begin
if (rr) begin
rd <= 32'h87654321;
end else if (re) begin
rd[7:0] <= mem[{ra, 2'b00}];
rd[15:8] <= mem[{ra, 2'b01}];
rd[23:16] <= mem[{ra, 2'b10}];
rd[31:24] <= mem[{ra, 2'b11}];
if (we && wa == {ra, 2'b00})
rd [7:0] <= wd;
if (we && wa == {ra, 2'b01})
rd [15:8] <= wd;
end
end
always @(posedge clk) begin
if (we)
mem[wa] <= wd;
end
endmodule

32
tests/memories/wide_read_sync.v Normal file
View file

@ -0,0 +1,32 @@
// expect-wr-ports 1
// expect-rd-ports 4
// expect-rd-wide-continuation 4'1110
module test(
input clk,
input re,
input we,
input [5:0] ra,
input [7:0] wa,
input [7:0] wd,
output reg [31:0] rd
);
reg [7:0] mem[0:255];
always @(posedge clk) begin
if (re) begin
rd[7:0] <= mem[{ra, 2'b00}];
rd[15:8] <= mem[{ra, 2'b01}];
rd[23:16] <= mem[{ra, 2'b10}];
rd[31:24] <= mem[{ra, 2'b11}];
end
end
always @(posedge clk) begin
if (we)
mem[wa] <= wd;
end
endmodule

40
tests/memories/wide_read_trans.v Normal file
View file

@ -0,0 +1,40 @@
// expect-wr-ports 1
// expect-rd-ports 4
// expect-rd-wide-continuation 4'1110
module test(
input clk,
input re,
input we,
input [5:0] ra,
input [7:0] wa,
input [7:0] wd,
output reg [31:0] rd
);
reg [7:0] mem[0:255];
always @(posedge clk) begin
if (re) begin
rd[7:0] <= mem[{ra, 2'b00}];
rd[15:8] <= mem[{ra, 2'b01}];
rd[23:16] <= mem[{ra, 2'b10}];
rd[31:24] <= mem[{ra, 2'b11}];
if (we && wa == {ra, 2'b00})
rd [7:0] <= wd;
if (we && wa == {ra, 2'b01})
rd [15:8] <= wd;
if (we && wa == {ra, 2'b10})
rd [23:16] <= wd;
if (we && wa == {ra, 2'b11})
rd [31:24] <= wd;
end
end
always @(posedge clk) begin
if (we)
mem[wa] <= wd;
end
endmodule

29
tests/memories/wide_thru_priority.v Normal file
View file

@ -0,0 +1,29 @@
// expect-wr-ports 3
// expect-rd-ports 1
// expect-wr-wide-continuation 3'010
module test(
input clk,
input we1, we2,
input [5:0] ra,
input [4:0] wa1,
input [5:0] wa2,
input [15:0] wd1,
input [7:0] wd2,
output [7:0] rd
);
reg [7:0] mem[0:63];
assign rd = mem[ra];
always @(posedge clk) begin
if (we1)
mem[{wa1, 1'b0}] <= wd1[7:0];
if (we2)
mem[wa2] <= wd2;
if (we1)
mem[{wa1, 1'b1}] <= wd1[15:8];
end
endmodule

29
tests/memories/wide_write.v Normal file
View file

@ -0,0 +1,29 @@
// expect-wr-ports 4
// expect-rd-ports 1
// expect-wr-wide-continuation 4'1110
module test(
input clk,
input [3:0] we,
input [7:0] ra,
input [5:0] wa,
input [31:0] wd,
output [7:0] rd
);
reg [7:0] mem[0:255];
assign rd = mem[ra];
always @(posedge clk) begin
if (we[0])
mem[{wa, 2'b00}] <= wd[7:0];
if (we[1])
mem[{wa, 2'b01}] <= wd[15:8];
if (we[2])
mem[{wa, 2'b10}] <= wd[23:16];
if (we[3])
mem[{wa, 2'b11}] <= wd[31:24];
end
endmodule

12
tests/opt/memory_dff_trans.ys
View file

@ -759,6 +759,10 @@ memory_dff
memory_collect
select -assert-count 1 t:$mem_v2
select -assert-count 1 t:$mem_v2 r:RD_TRANSPARENCY_MASK=4'b1111 r:RD_COLLISION_X_MASK=4'b0000 %i %i
memory_share
select -assert-count 1 t:$mem_v2
select -assert-count 1 t:$mem_v2 r:RD_TRANSPARENCY_MASK=4'b1111 r:RD_COLLISION_X_MASK=4'b0000 %i %i
select -assert-count 1 t:$mem_v2 r:RD_WIDE_CONTINUATION=4'b1110 %i
design -reset
@ -808,6 +812,10 @@ memory_dff
memory_collect
select -assert-count 1 t:$mem_v2
select -assert-count 1 t:$mem_v2 r:RD_TRANSPARENCY_MASK=4'b1111 r:RD_COLLISION_X_MASK=4'b0000 %i %i
memory_share
select -assert-count 1 t:$mem_v2
select -assert-count 1 t:$mem_v2 r:RD_TRANSPARENCY_MASK=4'b1111 r:RD_COLLISION_X_MASK=4'b0000 %i %i
select -assert-count 1 t:$mem_v2 r:WR_WIDE_CONTINUATION=4'b1110 %i
design -reset
@ -858,5 +866,9 @@ select -assert-count 1 t:$memrd_v2 r:TRANSPARENCY_MASK=4'b0001 r:COLLISION_X_MAS
select -assert-count 1 t:$memrd_v2 r:TRANSPARENCY_MASK=4'b0010 r:COLLISION_X_MASK=4'b1101 %i %i
select -assert-count 1 t:$memrd_v2 r:TRANSPARENCY_MASK=4'b0100 r:COLLISION_X_MASK=4'b1011 %i %i
select -assert-count 1 t:$memrd_v2 r:TRANSPARENCY_MASK=4'b1000 r:COLLISION_X_MASK=4'b0111 %i %i
memory_share
select -assert-count 1 t:$memrd_v2
select -assert-count 1 t:$memwr_v2
select -assert-count 1 t:$memrd_v2 r:TRANSPARENCY_MASK=1'b1 r:COLLISION_X_MASK=1'b0 %i %i
design -reset

6
tests/opt/opt_mem_priority.ys
View file

@ -200,6 +200,10 @@ EOT
hierarchy -auto-top
proc
opt
memory -nomap
opt_mem_priority
memory_collect
select -assert-count 1 t:$mem_v2
select -assert-count 1 t:$mem_v2 r:WR_PRIORITY_MASK=64'h0804020100000000 %i
memory_share
select -assert-count 1 t:$mem_v2 r:WR_PRIORITY_MASK=64'h0f0f0f0f00000000 %i
select -assert-count 1 t:$mem_v2 r:WR_WIDE_CONTINUATION=8'hee %i