mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-12 20:18:20 +00:00
Code Activity

Added "chparam -list"

Browse source
This commit is contained in:
Clifford Wolf 2015-04-07 19:21:30 +02:00
parent 590f74d8f0
commit 1f33b2a490
1 changed files with 21 additions and 0 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

21
passes/cmds/setattr.cc
View file

@ -192,11 +192,17 @@ struct ChparamPass : public Pass {
log("Re-evaluate the selected modules with new parameters. String values must be\n"); log("Re-evaluate the selected modules with new parameters. String values must be\n");
log("passed in double quotes (\").\n"); log("passed in double quotes (\").\n");
log("\n"); log("\n");
log("\n");
log(" chparam -list [selection]\n");
log("\n");
log("List the available parameters of the selected modules.\n");
log("\n");
} }
virtual void execute(std::vector<std::string> args, RTLIL::Design *design) virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
{ {
std::vector<setunset_t> setunset_list; std::vector<setunset_t> setunset_list;
dict<RTLIL::IdString, RTLIL::Const> new_parameters; dict<RTLIL::IdString, RTLIL::Const> new_parameters;
bool list_mode = false;
size_t argidx; size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++) for (argidx = 1; argidx < args.size(); argidx++)
@ -209,10 +215,25 @@ struct ChparamPass : public Pass {
argidx--; argidx--;
continue; continue;
} }
if (arg == "-list") {
list_mode = true;
continue;
}
break; break;
} }
extra_args(args, argidx, design); extra_args(args, argidx, design);
if (list_mode) {
if (!new_parameters.empty())
log_cmd_error("The options -set and -list cannot be used together.\n");
for (auto module : design->selected_modules()) {
log("%s:\n", log_id(module));
for (auto param : module->avail_parameters)
log(" %s\n", log_id(param));
}
return;
}
pool<IdString> modnames, old_modnames; pool<IdString> modnames, old_modnames;
for (auto module : design->selected_modules()) { for (auto module : design->selected_modules()) {
if (design->selected_whole_module(module)) if (design->selected_whole_module(module))