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Merge pull request #802 from whitequark/write_verilog_async_mem_ports
write_verilog: correctly emit asynchronous transparent ports
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commit
1f2548a564
1 changed files with 41 additions and 38 deletions
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@ -1065,6 +1065,8 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
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use_rd_clk = cell->parameters["\\RD_CLK_ENABLE"].extract(i).as_bool();
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rd_clk_posedge = cell->parameters["\\RD_CLK_POLARITY"].extract(i).as_bool();
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rd_transparent = cell->parameters["\\RD_TRANSPARENT"].extract(i).as_bool();
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if (use_rd_clk)
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{
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{
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std::ostringstream os;
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dump_sigspec(os, sig_rd_clk);
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@ -1072,7 +1074,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
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if( clk_to_lof_body.count(clk_domain_str) == 0 )
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clk_to_lof_body[clk_domain_str] = std::vector<std::string>();
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}
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if (use_rd_clk && !rd_transparent)
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if (!rd_transparent)
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{
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// for clocked read ports make something like:
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// reg [..] temp_id;
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@ -1100,8 +1102,9 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
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std::string line = stringf("assign %s = %s;\n", os.str().c_str(), temp_id.c_str());
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clk_to_lof_body[""].push_back(line);
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}
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} else {
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if (rd_transparent) {
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}
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else
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{
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// for rd-transparent read-ports make something like:
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// reg [..] temp_id;
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// always @(posedge clk)
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@ -1121,6 +1124,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
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std::string line = stringf("assign %s = %s[%s];\n", os.str().c_str(), mem_id.c_str(), temp_id.c_str());
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clk_to_lof_body[""].push_back(line);
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}
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}
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} else {
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// for non-clocked read-ports make something like:
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// assign r_data = array_reg[r_addr];
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@ -1131,7 +1135,6 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
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clk_to_lof_body[""].push_back(line);
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}
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}
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}
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int nwrite_ports = cell->parameters["\\WR_PORTS"].as_int();
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RTLIL::SigSpec sig_wr_clk, sig_wr_data, sig_wr_addr, sig_wr_en;
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