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Added non-std verilog assume() statement

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Clifford Wolf 2015-02-26 18:47:39 +01:00
parent b005eedf36
commit 1f1deda888
10 changed files with 67 additions and 25 deletions
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2
passes/opt/opt_clean.cc
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@ -47,7 +47,7 @@ void rmunused_module_cells(Module *module, bool verbose)
if (bit.wire != nullptr)
wire2driver[bit].insert(cell);
}
if (cell->type.in("$memwr", "$meminit", "$assert") || cell->has_keep_attr())
if (cell->type.in("$memwr", "$meminit", "$assert", "$assume") || cell->has_keep_attr())
queue.insert(cell);
else
unused.insert(cell);