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https://github.com/YosysHQ/yosys
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Added non-std verilog assume() statement
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parent
b005eedf36
commit
1f1deda888
10 changed files with 67 additions and 25 deletions
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@ -90,6 +90,7 @@ std::string AST::type2str(AstNodeType type)
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X(AST_IDENTIFIER)
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X(AST_PREFIX)
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X(AST_ASSERT)
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X(AST_ASSUME)
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X(AST_FCALL)
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X(AST_TO_BITS)
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X(AST_TO_SIGNED)
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@ -64,6 +64,7 @@ namespace AST
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AST_IDENTIFIER,
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AST_PREFIX,
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AST_ASSERT,
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AST_ASSUME,
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AST_FCALL,
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AST_TO_BITS,
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@ -1265,19 +1265,22 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
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// generate $assert cells
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case AST_ASSERT:
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case AST_ASSUME:
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{
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log_assert(children.size() == 2);
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RTLIL::SigSpec check = children[0]->genRTLIL();
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log_assert(check.size() == 1);
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if (GetSize(check) != 1)
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check = current_module->ReduceBool(NEW_ID, check);
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RTLIL::SigSpec en = children[1]->genRTLIL();
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log_assert(en.size() == 1);
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if (GetSize(en) != 1)
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en = current_module->ReduceBool(NEW_ID, en);
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std::stringstream sstr;
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sstr << "$assert$" << filename << ":" << linenum << "$" << (autoidx++);
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sstr << (type == AST_ASSERT ? "$assert$" : "$assume$") << filename << ":" << linenum << "$" << (autoidx++);
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RTLIL::Cell *cell = current_module->addCell(sstr.str(), "$assert");
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RTLIL::Cell *cell = current_module->addCell(sstr.str(), type == AST_ASSERT ? "$assert" : "$assume");
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cell->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
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for (auto &attr : attributes) {
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@ -1211,7 +1211,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
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}
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skip_dynamic_range_lvalue_expansion:;
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if (stage > 1 && type == AST_ASSERT && current_block != NULL)
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if (stage > 1 && (type == AST_ASSERT || type == AST_ASSUME) && current_block != NULL)
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{
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std::stringstream sstr;
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sstr << "$assert$" << filename << ":" << linenum << "$" << (autoidx++);
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@ -1255,7 +1255,7 @@ skip_dynamic_range_lvalue_expansion:;
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newNode->children.push_back(assign_check);
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newNode->children.push_back(assign_en);
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AstNode *assertnode = new AstNode(AST_ASSERT);
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AstNode *assertnode = new AstNode(type);
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assertnode->children.push_back(new AstNode(AST_IDENTIFIER));
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assertnode->children.push_back(new AstNode(AST_IDENTIFIER));
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assertnode->children[0]->str = id_check;
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@ -1266,9 +1266,8 @@ skip_dynamic_range_lvalue_expansion:;
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goto apply_newNode;
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}
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if (stage > 1 && type == AST_ASSERT && children.size() == 1)
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if (stage > 1 && (type == AST_ASSERT || type == AST_ASSUME) && children.size() == 1)
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{
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children[0] = new AstNode(AST_REDUCE_BOOL, children[0]->clone());
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children.push_back(mkconst_int(1, false, 1));
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did_something = true;
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}
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