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dfflibmap: reproduce dffe test oddity

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This commit is contained in:
Emil J. Tywoniak 2024-12-09 13:49:38 +01:00
parent 52336369fa
commit 1f125a5c89
3 changed files with 44 additions and 6 deletions
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9
tests/techmap/dfflibmap-sim.v
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@ -20,3 +20,12 @@ always @(posedge CLK, posedge CLEAR, posedge PRESET)
assign QN = ~Q;
endmodule
module dffe(input CLK, EN, D, output reg Q, output QN);
always @(negedge CLK)
if (EN) Q <= D;
assign QN = ~Q;
endmodule

24
tests/techmap/dfflibmap.lib
View file

@ -52,4 +52,28 @@ library(test) {
function : "IQN";
}
}
cell (dffe) {
area : 6;
ff("IQ", "IQN") {
next_state : "(D&DE) | (IQ&!DE)";
clocked_on : "!CLK";
}
pin(D) {
direction : input;
}
pin(DE) {
direction : input;
}
pin(CLK) {
direction : input;
}
pin(Q) {
direction: output;
function : "IQ";
}
pin(QN) {
direction: output;
function : "IQN";
}
}
}

17
tests/techmap/dfflibmap.ys
View file

@ -1,14 +1,15 @@
# $_DFF_PP0_ ff1 (.C(C), .D(D), .R(R), .Q(Q[1]));
# $_DFF_PP1_ ff2 (.C(C), .D(D), .R(R), .Q(Q[2]));
# $_DFFSR_PPP_ ff3 (.C(C), .D(D), .R(R), .S(S), .Q(Q[3]));
# $_DFFSR_NNN_ ff4 (.C(C), .D(D), .R(R), .S(S), .Q(Q[4]));
read_verilog -icells <<EOT
module top(input C, D, S, R, output [9:0] Q);
module top(input C, D, E, S, R, output [11:0] Q);
$_DFF_P_ ff0 (.C(C), .D(D), .Q(Q[0]));
$_DFF_PP0_ ff1 (.C(C), .D(D), .R(R), .Q(Q[1]));
$_DFF_PP1_ ff2 (.C(C), .D(D), .R(R), .Q(Q[2]));
$_DFFSR_PPP_ ff3 (.C(C), .D(D), .R(R), .S(S), .Q(Q[3]));
$_DFFSR_NNN_ ff4 (.C(C), .D(D), .R(R), .S(S), .Q(Q[4]));
$_DFFE_PP_ ff5 (.C(C), .D(D), .E(E), .Q(Q[5]));
assign Q[9:5] = ~Q[4:0];
assign Q[11:6] = ~Q[5:0];
endmodule
@ -19,6 +20,10 @@ simplemap
design -save orig
read_liberty -lib dfflibmap.lib
dfflibmap -liberty dfflibmap.lib
stat
debug techmap -assert -wb -D EQUIV -autoproc -map dfflibmap-sim.v
equiv_opt -map dfflibmap-sim.v -assert -multiclock dfflibmap -liberty dfflibmap.lib
equiv_opt -map dfflibmap-sim.v -assert -multiclock dfflibmap -prepare -liberty dfflibmap.lib