Bump yosys to latest

tests/peepopt/.gitignore

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+/*.log

tests/sim/sim_cycles.ys

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+read_verilog dff.v
+prep
+
+# create fst with 20 clock cycles (41 samples, 202ns)
+sim -clock clk -fst sim_cycles.fst -n 20
+
+logger -expect-no-warnings
+
+# final step is 41
+logger -expect log "Co-simulating cycle 41" 2
+logger -warn "Co-simulating cycle 42"
+sim -clock clk -r sim_cycles.fst -scope dff -n 21 -sim-cmp
+sim -clock clk -r sim_cycles.fst -scope dff -stop 202 -sim-cmp
+logger -check-expected
+
+# over limit stops at final step
+logger -expect log "Co-simulating cycle 41" 2
+sim -clock clk -r sim_cycles.fst -scope dff -n 30 -sim-cmp
+# -stop warns for over limit
+logger -nowarn "Stop time is after simulation file end time"
+sim -clock clk -r sim_cycles.fst -scope dff -stop 300 -sim-cmp
+logger -check-expected
+
+# don't auto step last
+logger -expect log "Co-simulating cycle 40" 2
+logger -warn "Co-simulating cycle 41"
+sim -clock clk -r sim_cycles.fst -scope dff -n 20 -sim-cmp
+sim -clock clk -r sim_cycles.fst -scope dff -stop 200 -sim-cmp
+logger -check-expected
+
+# -n 10 == -stop 100
+# should simulate up to 20 and not more
+logger -expect log "Co-simulating cycle 20" 2
+logger -warn "Co-simulating cycle 21"
+sim -clock clk -r sim_cycles.fst -scope dff -n 10 -sim-cmp
+sim -clock clk -r sim_cycles.fst -scope dff -stop 100 -sim-cmp
+logger -check-expected
+
+# -n 1 == -stop 10
+logger -expect log "Co-simulating cycle 2" 2
+logger -warn "Co-simulating cycle 3"
+sim -clock clk -r sim_cycles.fst -scope dff -n 1 -sim-cmp
+sim -clock clk -r sim_cycles.fst -scope dff -stop 10 -sim-cmp
+logger -check-expected
+
+# -n 0 == -stop 0
+logger -expect log "Co-simulating cycle 0" 2
+logger -warn "Co-simulating cycle 1"
+sim -clock clk -r sim_cycles.fst -scope dff -n 0 -sim-cmp
+sim -clock clk -r sim_cycles.fst -scope dff -stop 0 -sim-cmp
+logger -check-expected

tests/various/cutpoint_whole.ys

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+read_verilog << EOT
+module top(input a, b, output o);
+    wire c, d, e;
+    bb bb1 (.a (a), .b (b), .o (c));
+    sub_mod sub_inst (.a (a), .b (b), .o (e));
+    some_mod some_inst (.a (c), .b (d), .c (e), .o (o));
+endmodule
+
+(* blackbox *)
+module bb #( parameter SOME_PARAM=0 ) (input a, b, output o);
+endmodule
+
+module sub_mod(input a, b, output o);
+    bb bb2 (.a (a), .b (b), .o (o));
+endmodule
+
+module some_mod(input a, b, c, output o);
+assign o = a & (b | c);
+endmodule
+EOT
+
+hierarchy -top top
+design -stash hier
+
+# removing cell
+design -load hier
+logger -expect log "Removing cell .*, making all cell outputs cutpoints" 1
+cutpoint sub_mod/bb2
+logger -check-expected
+logger -werror "Removing cell .*, making all cell outputs cutpoints"
+
+# removing wires
+design -load hier
+logger -expect log "Making wire .* a cutpoint" 1
+cutpoint top/c
+logger -check-expected
+logger -werror "Making wire .* a cutpoint"
+
+# removing output wires
+design -load hier
+logger -expect log "Making output wire .* a cutpoint" 1
+cutpoint sub_mod/o
+logger -check-expected
+logger -werror "Making output wire .* a cutpoint"
+
+# whole module optimization, doesn't do any of the previous
+design -load hier
+logger -expect log "Making all outputs of module .* cut points, removing module contents" 1
+cutpoint sub_mod
+logger -check-expected