mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-05-09 08:45:48 +00:00
Code Activity

Resolve reg naming to some extent

Browse source
This commit is contained in:
Akash Levy 2024-12-17 12:11:39 -08:00
parent 2d105fc2c3
commit 1eee11846e
5 changed files with 97 additions and 90 deletions
Download patch file Download diff file Expand all files Collapse all files

1
frontends/verific/verific.h
View file

@ -82,6 +82,7 @@ struct VerificImporter
RTLIL::SigBit net_map_at(Verific::Net *net);
RTLIL::IdString new_verific_id(Verific::DesignObj *obj);
RTLIL::IdString new_verific_id_suffix(RTLIL::IdString id, const char *suffix);
void import_attributes(dict<RTLIL::IdString, RTLIL::Const> &attributes, Verific::DesignObj *obj, Verific::Netlist *nl = nullptr, int wire_width_hint = -1);
RTLIL::SigBit netToSigBit(Verific::Net *net);