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Test fixes for latest iverilog

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This commit is contained in:
Miodrag Milanovic 2022-09-21 15:46:43 +02:00
parent a217450524
commit 1ecf6aee9b
3 changed files with 14 additions and 5 deletions
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3
techlibs/achronix/speedster22i/cells_sim.v
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@ -68,9 +68,8 @@ end
assign dout = combout_rt & 1'b1;
endmodule
module DFF (output q,
module DFF (output reg q,
input d, ck);
reg q;
always @(posedge ck)
q <= d;

2
techlibs/sf2/cells_sim.v
View file

@ -162,7 +162,7 @@ module ARI1 (
wire F1 = INIT[8 + Fsel];
wire Yout = A ? F1 : F0;
assign Y = Yout;
wire S = FCI ^ Yout;
assign S = FCI ^ Yout;
wire G = INIT[16] ? (INIT[17] ? F1 : F0) : INIT[17];
wire P = INIT[19] ? 1'b1 : (INIT[18] ? Yout : 1'b0);
assign FCO = P ? FCI : G;

14
tests/simple/memory.v
View file

@ -137,8 +137,13 @@ endmodule
// ----------------------------------------------------------
module memtest06_sync(input clk, input rst, input [2:0] idx, input [7:0] din, output [7:0] dout);
module memtest06_sync(clk, rst, idx, din, dout);
input clk;
input rst;
(* gentb_constant=0 *) wire rst;
input [2:0] idx;
input [7:0] din;
output [7:0] dout;
reg [7:0] test [0:7];
integer i;
always @(posedge clk) begin
@ -156,8 +161,13 @@ module memtest06_sync(input clk, input rst, input [2:0] idx, input [7:0] din, ou
assign dout = test[idx];
endmodule
module memtest06_async(input clk, input rst, input [2:0] idx, input [7:0] din, output [7:0] dout);
module memtest06_async(clk, rst, idx, din, dout);
input clk;
input rst;
(* gentb_constant=0 *) wire rst;
input [2:0] idx;
input [7:0] din;
output [7:0] dout;
reg [7:0] test [0:7];
integer i;
always @(posedge clk or posedge rst) begin