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Test fixes for latest iverilog

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This commit is contained in:
Miodrag Milanovic 2022-09-21 15:46:43 +02:00
parent a217450524
commit 1ecf6aee9b
3 changed files with 14 additions and 5 deletions
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14
tests/simple/memory.v
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@ -137,8 +137,13 @@ endmodule
// ----------------------------------------------------------
module memtest06_sync(input clk, input rst, input [2:0] idx, input [7:0] din, output [7:0] dout);
module memtest06_sync(clk, rst, idx, din, dout);
input clk;
input rst;
(* gentb_constant=0 *) wire rst;
input [2:0] idx;
input [7:0] din;
output [7:0] dout;
reg [7:0] test [0:7];
integer i;
always @(posedge clk) begin
@ -156,8 +161,13 @@ module memtest06_sync(input clk, input rst, input [2:0] idx, input [7:0] din, ou
assign dout = test[idx];
endmodule
module memtest06_async(input clk, input rst, input [2:0] idx, input [7:0] din, output [7:0] dout);
module memtest06_async(clk, rst, idx, din, dout);
input clk;
input rst;
(* gentb_constant=0 *) wire rst;
input [2:0] idx;
input [7:0] din;
output [7:0] dout;
reg [7:0] test [0:7];
integer i;
always @(posedge clk or posedge rst) begin