mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-08-09 20:50:51 +00:00
Code Activity

Test fixes for latest iverilog

Browse source
This commit is contained in:
Miodrag Milanovic 2022-09-21 15:46:43 +02:00
parent a217450524
commit 1ecf6aee9b
3 changed files with 14 additions and 5 deletions
Download patch file Download diff file Expand all files Collapse all files

3
techlibs/achronix/speedster22i/cells_sim.v
View file

@ -68,9 +68,8 @@ end
assign dout = combout_rt & 1'b1;
endmodule
module DFF (output q,
module DFF (output reg q,
input d, ck);
reg q;
always @(posedge ck)
q <= d;