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verilog: fix handling of nested ifdef directives

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- track depth so we know whether to consider higher-level elsifs
- error on unmatched endif/elsif/else
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Zachary Snow 2021-02-25 15:53:55 -05:00 • committed by Zachary Snow
parent b6904a8e53
commit 1ec5994100
8 changed files with 197 additions and 11 deletions
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tests/verilog/include_self.ys Normal file
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@ -0,0 +1,2 @@
read_verilog include_self.v
select -assert-count 1 top/x