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verilog: fix handling of nested ifdef directives

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- track depth so we know whether to consider higher-level elsifs
- error on unmatched endif/elsif/else
This commit is contained in:
Zachary Snow 2021-02-25 15:53:55 -05:00 • committed by Zachary Snow
parent b6904a8e53
commit 1ec5994100
8 changed files with 197 additions and 11 deletions
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88
tests/simple/ifdef_1.v Normal file
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@ -0,0 +1,88 @@
module top(o1, o2, o3, o4);
`define FAIL input wire not_a_port;
`ifdef COND_1
`FAIL
`elsif COND_2
`FAIL
`elsif COND_3
`FAIL
`elsif COND_4
`FAIL
`else
`define COND_4
output wire o4;
`ifdef COND_1
`FAIL
`elsif COND_2
`FAIL
`elsif COND_3
`FAIL
`elsif COND_4
`define COND_3
output wire o3;
`ifdef COND_1
`FAIL
`elsif COND_2
`FAIL
`elsif COND_3
`define COND_2
output wire o2;
`ifdef COND_1
`FAIL
`elsif COND_2
`define COND_1
output wire o1;
`ifdef COND_1
`ifdef COND_1
`elsif COND_2
`FAIL
`elsif COND_3
`FAIL
`elsif COND_4
`FAIL
`else
`FAIL
`endif
`elsif COND_2
`FAIL
`elsif COND_3
`FAIL
`elsif COND_4
`FAIL
`else
`FAIL
`endif
`elsif COND_3
`FAIL
`elsif COND_4
`FAIL
`else
`FAIL
`endif
`elsif COND_4
`FAIL
`else
`FAIL
`endif
`else
`FAIL
`endif
`endif
endmodule

21
tests/simple/ifdef_2.v Normal file
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module top(o1, o2, o3);
output wire o1;
`define COND_1
`define COND_2
`define COND_3
`ifdef COND_1
output wire o2;
`elsif COND_2
input wire dne1;
`elsif COND_3
input wire dne2;
`else
input wire dne3;
`endif
output wire o3;
endmodule