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rtlil: replace SigSig actions with new type SyncAction

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This commit is contained in:
Emil J. Tywoniak 2025-11-02 11:22:03 +01:00
parent 37875fdedf
commit 1eb696c786
19 changed files with 305 additions and 252 deletions
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17
passes/proc/proc_rom.cc
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@ -58,7 +58,7 @@ struct RomWorker
SigSpec lhs;
dict<SigBit, int> lhs_lookup;
for (auto &it: sw->cases[0]->actions) {
for (auto bit: it.first) {
for (auto bit: it.lhs) {
if (!lhs_lookup.count(bit)) {
lhs_lookup[bit] = GetSize(lhs);
lhs.append(bit);
@ -87,17 +87,17 @@ struct RomWorker
}
Const val = Const(State::Sm, GetSize(lhs));
for (auto &it: cs->actions) {
if (!it.second.is_fully_const()) {
if (!it.rhs.is_fully_const()) {
log_debug("rejecting switch: rhs not const\n");
return;
}
for (int i = 0; i < GetSize(it.first); i++) {
auto it2 = lhs_lookup.find(it.first[i]);
for (int i = 0; i < GetSize(it.lhs); i++) {
auto it2 = lhs_lookup.find(it.lhs[i]);
if (it2 == lhs_lookup.end()) {
log_debug("rejecting switch: lhs not uniform\n");
return;
}
val.set(it2->second, it.second[i].data);
val.set(it2->second, it.rhs[i].data);
}
}
for (auto bit: val) {
@ -193,19 +193,20 @@ struct RomWorker
delete cs;
sw->cases.clear();
sw->signal = sw->signal.extract(0, swsigbits);
Const action_src = mem.has_attribute(ID::src) ? mem.attributes[ID::src] : Const("");
if (abits == GetSize(sw->signal)) {
sw->signal = SigSpec();
RTLIL::CaseRule *cs = new RTLIL::CaseRule;
cs->actions.push_back(SigSig(lhs, rdata));
cs->actions.push_back({lhs, rdata});
sw->cases.push_back(cs);
} else {
sw->signal = sw->signal.extract_end(abits);
RTLIL::CaseRule *cs = new RTLIL::CaseRule;
cs->compare.push_back(Const(State::S0, GetSize(sw->signal)));
cs->actions.push_back(SigSig(lhs, rdata));
cs->actions.push_back({lhs, rdata});
sw->cases.push_back(cs);
RTLIL::CaseRule *cs2 = new RTLIL::CaseRule;
cs2->actions.push_back(SigSig(lhs, default_val));
cs2->actions.push_back({lhs, default_val});
sw->cases.push_back(cs2);
}