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https://github.com/YosysHQ/yosys
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rtlil: replace SigSig actions with new type SyncAction
This commit is contained in:
Emil J. Tywoniak
parent
37875fdedf
commit
1eb696c786
19 changed files with 305 additions and 252 deletions
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@ -98,7 +98,7 @@ struct SigSnippets
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void insert(const RTLIL::CaseRule *cs)
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{
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for (auto &action : cs->actions)
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insert(action.first);
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insert(action.lhs);
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for (auto sw : cs->switches)
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for (auto cs2 : sw->cases)
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@ -121,7 +121,7 @@ struct SnippetSwCache
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void insert(const RTLIL::CaseRule *cs, vector<RTLIL::SwitchRule*> &sw_stack)
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{
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for (auto &action : cs->actions)
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for (auto bit : action.first) {
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for (auto bit : action.lhs) {
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int sn = snippets->bit2snippet.at(bit, -1);
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if (sn < 0)
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continue;
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@ -150,130 +150,138 @@ void apply_attrs(RTLIL::Cell *cell, const RTLIL::SwitchRule *sw, const RTLIL::Ca
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cell->add_strpool_attribute(ID::src, cs->get_strpool_attribute(ID::src));
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}
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RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const std::vector<RTLIL::SigSpec> &compare, RTLIL::SwitchRule *sw, RTLIL::CaseRule *cs, bool ifxmode)
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{
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std::stringstream sstr;
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sstr << "$procmux$" << (autoidx++);
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struct MuxGenCtx {
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RTLIL::Module *mod;
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const RTLIL::SigSpec &signal;
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const std::vector<RTLIL::SigSpec> *compare;
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RTLIL::Cell *last_mux_cell;
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RTLIL::SwitchRule *sw;
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RTLIL::CaseRule *cs;
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bool ifxmode;
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RTLIL::Wire *cmp_wire = mod->addWire(sstr.str() + "_CMP", 0);
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RTLIL::SigSpec gen_cmp() {
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std::stringstream sstr;
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sstr << "$procmux$" << (autoidx++);
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for (auto comp : compare)
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{
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RTLIL::SigSpec sig = signal;
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RTLIL::Wire *cmp_wire = mod->addWire(sstr.str() + "_CMP", 0);
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// get rid of don't-care bits
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log_assert(sig.size() == comp.size());
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for (int i = 0; i < comp.size(); i++)
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if (comp[i] == RTLIL::State::Sa) {
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sig.remove(i);
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comp.remove(i--);
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}
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if (comp.size() == 0)
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return RTLIL::SigSpec();
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if (sig.size() == 1 && comp == RTLIL::SigSpec(1,1) && !ifxmode)
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for (auto comp : *compare)
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{
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mod->connect(RTLIL::SigSig(RTLIL::SigSpec(cmp_wire, cmp_wire->width++), sig));
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RTLIL::SigSpec sig = signal;
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// get rid of don't-care bits
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log_assert(sig.size() == comp.size());
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for (int i = 0; i < comp.size(); i++)
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if (comp[i] == RTLIL::State::Sa) {
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sig.remove(i);
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comp.remove(i--);
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}
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if (comp.size() == 0)
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return RTLIL::SigSpec();
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if (sig.size() == 1 && comp == RTLIL::SigSpec(1,1) && !ifxmode)
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{
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mod->connect(RTLIL::SigSig(RTLIL::SigSpec(cmp_wire, cmp_wire->width++), sig));
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}
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else
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{
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// create compare cell
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RTLIL::Cell *eq_cell = mod->addCell(stringf("%s_CMP%d", sstr.str(), cmp_wire->width), ifxmode ? ID($eqx) : ID($eq));
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apply_attrs(eq_cell, sw, cs);
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eq_cell->parameters[ID::A_SIGNED] = RTLIL::Const(0);
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eq_cell->parameters[ID::B_SIGNED] = RTLIL::Const(0);
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eq_cell->parameters[ID::A_WIDTH] = RTLIL::Const(sig.size());
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eq_cell->parameters[ID::B_WIDTH] = RTLIL::Const(comp.size());
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eq_cell->parameters[ID::Y_WIDTH] = RTLIL::Const(1);
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eq_cell->setPort(ID::A, sig);
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eq_cell->setPort(ID::B, comp);
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eq_cell->setPort(ID::Y, RTLIL::SigSpec(cmp_wire, cmp_wire->width++));
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}
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}
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RTLIL::Wire *ctrl_wire;
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if (cmp_wire->width == 1)
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{
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ctrl_wire = cmp_wire;
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}
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else
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{
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// create compare cell
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RTLIL::Cell *eq_cell = mod->addCell(stringf("%s_CMP%d", sstr.str(), cmp_wire->width), ifxmode ? ID($eqx) : ID($eq));
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apply_attrs(eq_cell, sw, cs);
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ctrl_wire = mod->addWire(sstr.str() + "_CTRL");
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eq_cell->parameters[ID::A_SIGNED] = RTLIL::Const(0);
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eq_cell->parameters[ID::B_SIGNED] = RTLIL::Const(0);
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// reduce cmp vector to one logic signal
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RTLIL::Cell *any_cell = mod->addCell(sstr.str() + "_ANY", ID($reduce_or));
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apply_attrs(any_cell, sw, cs);
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eq_cell->parameters[ID::A_WIDTH] = RTLIL::Const(sig.size());
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eq_cell->parameters[ID::B_WIDTH] = RTLIL::Const(comp.size());
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eq_cell->parameters[ID::Y_WIDTH] = RTLIL::Const(1);
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any_cell->parameters[ID::A_SIGNED] = RTLIL::Const(0);
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any_cell->parameters[ID::A_WIDTH] = RTLIL::Const(cmp_wire->width);
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any_cell->parameters[ID::Y_WIDTH] = RTLIL::Const(1);
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eq_cell->setPort(ID::A, sig);
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eq_cell->setPort(ID::B, comp);
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eq_cell->setPort(ID::Y, RTLIL::SigSpec(cmp_wire, cmp_wire->width++));
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any_cell->setPort(ID::A, cmp_wire);
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any_cell->setPort(ID::Y, RTLIL::SigSpec(ctrl_wire));
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}
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return RTLIL::SigSpec(ctrl_wire);
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}
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RTLIL::Wire *ctrl_wire;
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if (cmp_wire->width == 1)
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{
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ctrl_wire = cmp_wire;
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}
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else
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{
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ctrl_wire = mod->addWire(sstr.str() + "_CTRL");
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RTLIL::SigSpec gen_mux(RTLIL::SigSpec when_signal, RTLIL::SigSpec else_signal) {
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log_assert(when_signal.size() == else_signal.size());
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// reduce cmp vector to one logic signal
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RTLIL::Cell *any_cell = mod->addCell(sstr.str() + "_ANY", ID($reduce_or));
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apply_attrs(any_cell, sw, cs);
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std::stringstream sstr;
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sstr << "$procmux$" << (autoidx++);
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any_cell->parameters[ID::A_SIGNED] = RTLIL::Const(0);
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any_cell->parameters[ID::A_WIDTH] = RTLIL::Const(cmp_wire->width);
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any_cell->parameters[ID::Y_WIDTH] = RTLIL::Const(1);
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// the trivial cases
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if (compare->size() == 0 || when_signal == else_signal)
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return when_signal;
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any_cell->setPort(ID::A, cmp_wire);
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any_cell->setPort(ID::Y, RTLIL::SigSpec(ctrl_wire));
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// compare results
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RTLIL::SigSpec ctrl_sig = gen_cmp();
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if (ctrl_sig.size() == 0)
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return when_signal;
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log_assert(ctrl_sig.size() == 1);
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// prepare multiplexer output signal
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RTLIL::Wire *result_wire = mod->addWire(sstr.str() + "_Y", when_signal.size());
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// create the multiplexer itself
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RTLIL::Cell *mux_cell = mod->addCell(sstr.str(), ID($mux));
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apply_attrs(mux_cell, sw, cs);
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mux_cell->parameters[ID::WIDTH] = RTLIL::Const(when_signal.size());
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mux_cell->setPort(ID::A, else_signal);
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mux_cell->setPort(ID::B, when_signal);
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mux_cell->setPort(ID::S, ctrl_sig);
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mux_cell->setPort(ID::Y, RTLIL::SigSpec(result_wire));
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last_mux_cell = mux_cell;
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return RTLIL::SigSpec(result_wire);
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}
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return RTLIL::SigSpec(ctrl_wire);
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}
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void append_pmux(RTLIL::SigSpec when_signal) {
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log_assert(last_mux_cell != NULL);
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log_assert(when_signal.size() == last_mux_cell->getPort(ID::A).size());
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RTLIL::SigSpec gen_mux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const std::vector<RTLIL::SigSpec> &compare, RTLIL::SigSpec when_signal, RTLIL::SigSpec else_signal, RTLIL::Cell *&last_mux_cell, RTLIL::SwitchRule *sw, RTLIL::CaseRule *cs, bool ifxmode)
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{
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log_assert(when_signal.size() == else_signal.size());
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if (when_signal == last_mux_cell->getPort(ID::A))
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return;
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std::stringstream sstr;
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sstr << "$procmux$" << (autoidx++);
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RTLIL::SigSpec ctrl_sig = gen_cmp();
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log_assert(ctrl_sig.size() == 1);
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last_mux_cell->type = ID($pmux);
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// the trivial cases
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if (compare.size() == 0 || when_signal == else_signal)
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return when_signal;
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RTLIL::SigSpec new_s = last_mux_cell->getPort(ID::S);
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new_s.append(ctrl_sig);
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last_mux_cell->setPort(ID::S, new_s);
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// compare results
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RTLIL::SigSpec ctrl_sig = gen_cmp(mod, signal, compare, sw, cs, ifxmode);
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if (ctrl_sig.size() == 0)
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return when_signal;
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log_assert(ctrl_sig.size() == 1);
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RTLIL::SigSpec new_b = last_mux_cell->getPort(ID::B);
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new_b.append(when_signal);
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last_mux_cell->setPort(ID::B, new_b);
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// prepare multiplexer output signal
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RTLIL::Wire *result_wire = mod->addWire(sstr.str() + "_Y", when_signal.size());
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last_mux_cell->parameters[ID::S_WIDTH] = last_mux_cell->getPort(ID::S).size();
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}
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// create the multiplexer itself
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RTLIL::Cell *mux_cell = mod->addCell(sstr.str(), ID($mux));
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apply_attrs(mux_cell, sw, cs);
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mux_cell->parameters[ID::WIDTH] = RTLIL::Const(when_signal.size());
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mux_cell->setPort(ID::A, else_signal);
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mux_cell->setPort(ID::B, when_signal);
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mux_cell->setPort(ID::S, ctrl_sig);
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mux_cell->setPort(ID::Y, RTLIL::SigSpec(result_wire));
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last_mux_cell = mux_cell;
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return RTLIL::SigSpec(result_wire);
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}
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void append_pmux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const std::vector<RTLIL::SigSpec> &compare, RTLIL::SigSpec when_signal, RTLIL::Cell *last_mux_cell, RTLIL::SwitchRule *sw, RTLIL::CaseRule *cs, bool ifxmode)
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{
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log_assert(last_mux_cell != NULL);
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log_assert(when_signal.size() == last_mux_cell->getPort(ID::A).size());
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if (when_signal == last_mux_cell->getPort(ID::A))
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return;
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RTLIL::SigSpec ctrl_sig = gen_cmp(mod, signal, compare, sw, cs, ifxmode);
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log_assert(ctrl_sig.size() == 1);
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last_mux_cell->type = ID($pmux);
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RTLIL::SigSpec new_s = last_mux_cell->getPort(ID::S);
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new_s.append(ctrl_sig);
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last_mux_cell->setPort(ID::S, new_s);
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RTLIL::SigSpec new_b = last_mux_cell->getPort(ID::B);
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new_b.append(when_signal);
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last_mux_cell->setPort(ID::B, new_b);
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last_mux_cell->parameters[ID::S_WIDTH] = last_mux_cell->getPort(ID::S).size();
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}
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};
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const pool<SigBit> &get_full_case_bits(SnippetSwCache &swcache, RTLIL::SwitchRule *sw)
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{
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@ -290,7 +298,7 @@ const pool<SigBit> &get_full_case_bits(SnippetSwCache &swcache, RTLIL::SwitchRul
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pool<SigBit> case_bits;
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for (auto it : cs->actions) {
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for (auto bit : it.first)
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for (auto bit : it.lhs)
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case_bits.insert(bit);
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}
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@ -317,20 +325,28 @@ const pool<SigBit> &get_full_case_bits(SnippetSwCache &swcache, RTLIL::SwitchRul
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return swcache.full_case_bits_cache.at(sw);
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}
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struct MuxTreeContext {
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RTLIL::Module* mod;
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SnippetSwCache& swcache;
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dict<RTLIL::SwitchRule*, bool> &swpara;
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RTLIL::CaseRule *cs;
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const RTLIL::SigSpec &sig;
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RTLIL::SigSpec defval;
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const bool ifxmode;
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};
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RTLIL::SigSpec signal_to_mux_tree(RTLIL::Module *mod, SnippetSwCache &swcache, dict<RTLIL::SwitchRule*, bool> &swpara,
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RTLIL::CaseRule *cs, const RTLIL::SigSpec &sig, const RTLIL::SigSpec &defval, bool ifxmode)
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RTLIL::SigSpec signal_to_mux_tree(MuxTreeContext ctx)
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{
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RTLIL::SigSpec result = defval;
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RTLIL::SigSpec result = ctx.defval;
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for (auto &action : cs->actions) {
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sig.replace(action.first, action.second, &result);
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action.first.remove2(sig, &action.second);
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for (auto &action : ctx.cs->actions) {
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ctx.sig.replace(action.lhs, action.rhs, &result);
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action.lhs.remove2(ctx.sig, &action.rhs);
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}
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for (auto sw : cs->switches)
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for (auto sw : ctx.cs->switches)
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{
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if (!swcache.check(sw))
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if (!ctx.swcache.check(sw))
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continue;
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// detect groups of parallel cases
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@ -338,7 +354,7 @@ RTLIL::SigSpec signal_to_mux_tree(RTLIL::Module *mod, SnippetSwCache &swcache, d
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bool is_simple_parallel_case = true;
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if (!sw->get_bool_attribute(ID::parallel_case)) {
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if (!swpara.count(sw)) {
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if (!ctx.swpara.count(sw)) {
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pool<Const> case_values;
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for (size_t i = 0; i < sw->cases.size(); i++) {
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RTLIL::CaseRule *cs2 = sw->cases[i];
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@ -354,9 +370,9 @@ RTLIL::SigSpec signal_to_mux_tree(RTLIL::Module *mod, SnippetSwCache &swcache, d
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if (0)
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not_simple_parallel_case:
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is_simple_parallel_case = false;
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swpara[sw] = is_simple_parallel_case;
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ctx.swpara[sw] = is_simple_parallel_case;
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} else {
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is_simple_parallel_case = swpara.at(sw);
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is_simple_parallel_case = ctx.swpara.at(sw);
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}
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}
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@ -382,28 +398,40 @@ RTLIL::SigSpec signal_to_mux_tree(RTLIL::Module *mod, SnippetSwCache &swcache, d
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for (auto pat : cs2->compare)
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if (!pat.is_fully_const())
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extra_group_for_next_case = true;
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else if (!ifxmode)
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else if (!ctx.ifxmode)
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pool.take(pat);
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}
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}
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// mask default bits that are irrelevant because the output is driven by a full case
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const pool<SigBit> &full_case_bits = get_full_case_bits(swcache, sw);
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for (int i = 0; i < GetSize(sig); i++)
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if (full_case_bits.count(sig[i]))
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const pool<SigBit> &full_case_bits = get_full_case_bits(ctx.swcache, sw);
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for (int i = 0; i < GetSize(ctx.sig); i++)
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if (full_case_bits.count(ctx.sig[i]))
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result[i] = State::Sx;
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// evaluate in reverse order to give the first entry the top priority
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RTLIL::SigSpec initial_val = result;
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RTLIL::Cell *last_mux_cell = NULL;
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MuxGenCtx mux_gen_ctx {ctx.mod,
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sw->signal,
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nullptr,
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nullptr,
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sw,
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nullptr,
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ctx.ifxmode
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};
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// evaluate in reverse order to give the first entry the top priority
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for (size_t i = 0; i < sw->cases.size(); i++) {
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int case_idx = sw->cases.size() - i - 1;
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RTLIL::CaseRule *cs2 = sw->cases[case_idx];
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RTLIL::SigSpec value = signal_to_mux_tree(mod, swcache, swpara, cs2, sig, initial_val, ifxmode);
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if (last_mux_cell && pgroups[case_idx] == pgroups[case_idx+1])
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append_pmux(mod, sw->signal, cs2->compare, value, last_mux_cell, sw, cs2, ifxmode);
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else
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result = gen_mux(mod, sw->signal, cs2->compare, value, result, last_mux_cell, sw, cs2, ifxmode);
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MuxTreeContext new_ctx = ctx;
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new_ctx.cs = sw->cases[case_idx];
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new_ctx.defval = initial_val;
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RTLIL::SigSpec value = signal_to_mux_tree(new_ctx);
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mux_gen_ctx.cs = new_ctx.cs;
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mux_gen_ctx.compare = &new_ctx.cs->compare;
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if (mux_gen_ctx.last_mux_cell && pgroups[case_idx] == pgroups[case_idx+1]) {
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mux_gen_ctx.append_pmux(value);
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} else {
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result = mux_gen_ctx.gen_mux(value, result);
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}
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}
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}
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@ -429,9 +457,17 @@ void proc_mux(RTLIL::Module *mod, RTLIL::Process *proc, bool ifxmode)
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swcache.current_snippet = idx;
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RTLIL::SigSpec sig = sigsnip.sigidx[idx];
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log("%6d/%d: %s\n", ++cnt, GetSize(sigsnip.snippets), log_signal(sig));
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log_debug("%6d/%d: %s\n", ++cnt, GetSize(sigsnip.snippets), log_signal(sig));
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RTLIL::SigSpec value = signal_to_mux_tree(mod, swcache, swpara, &proc->root_case, sig, RTLIL::SigSpec(RTLIL::State::Sx, sig.size()), ifxmode);
|
||||
RTLIL::SigSpec value = signal_to_mux_tree({
|
||||
mod,
|
||||
swcache,
|
||||
swpara,
|
||||
&proc->root_case,
|
||||
sig,
|
||||
RTLIL::SigSpec(RTLIL::State::Sx, sig.size()),
|
||||
ifxmode
|
||||
});
|
||||
mod->connect(RTLIL::SigSig(sig, value));
|
||||
}
|
||||
}
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue