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rtlil: replace SigSig actions with new type SyncAction

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This commit is contained in:
Emil J. Tywoniak 2025-11-02 11:22:03 +01:00
parent 37875fdedf
commit 1eb696c786
19 changed files with 305 additions and 252 deletions
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4
passes/cmds/bugpoint.cc
View file

@ -361,7 +361,7 @@ struct BugpointPass : public Pass {
{
if (index++ == seed)
{
log_header(design, "Trying to remove assign %s %s in %s.%s.\n", log_signal(it->first), log_signal(it->second), log_id(mod), log_id(pr.first));
log_header(design, "Trying to remove assign %s %s in %s.%s.\n", log_signal(it->lhs), log_signal(it->rhs), log_id(mod), log_id(pr.first));
cs->actions.erase(it);
return design_copy;
}
@ -387,7 +387,7 @@ struct BugpointPass : public Pass {
{
if (index++ == seed)
{
log_header(design, "Trying to remove sync %s update %s %s in %s.%s.\n", log_signal(sy->signal), log_signal(it->first), log_signal(it->second), log_id(mod), log_id(pr.first));
log_header(design, "Trying to remove sync %s update %s %s in %s.%s.\n", log_signal(sy->signal), log_signal(it->lhs), log_signal(it->rhs), log_id(mod), log_id(pr.first));
sy->actions.erase(it);
return design_copy;
}

12
passes/cmds/check.cc
View file

@ -130,12 +130,12 @@ struct CheckPass : public Pass {
std::vector<RTLIL::CaseRule*> all_cases = {&proc_it.second->root_case};
for (size_t i = 0; i < all_cases.size(); i++) {
for (auto action : all_cases[i]->actions) {
for (auto bit : sigmap(action.first))
for (auto bit : sigmap(action.lhs))
wire_drivers[bit].push_back(
stringf("action %s <= %s (case rule) in process %s",
log_signal(action.first), log_signal(action.second), log_id(proc_it.first)));
log_signal(action.lhs), log_signal(action.rhs), log_id(proc_it.first)));
for (auto bit : sigmap(action.second))
for (auto bit : sigmap(action.rhs))
if (bit.wire) used_wires.insert(bit);
}
for (auto switch_ : all_cases[i]->switches) {
@ -151,11 +151,11 @@ struct CheckPass : public Pass {
for (auto bit : sigmap(sync->signal))
if (bit.wire) used_wires.insert(bit);
for (auto action : sync->actions) {
for (auto bit : sigmap(action.first))
for (auto bit : sigmap(action.lhs))
wire_drivers[bit].push_back(
stringf("action %s <= %s (sync rule) in process %s",
log_signal(action.first), log_signal(action.second), log_id(proc_it.first)));
for (auto bit : sigmap(action.second))
log_signal(action.lhs), log_signal(action.rhs), log_id(proc_it.first)));
for (auto bit : sigmap(action.rhs))
if (bit.wire) used_wires.insert(bit);
}
for (auto memwr : sync->mem_write_actions) {

9
passes/cmds/clean_zerowidth.cc
View file

@ -17,6 +17,7 @@
*
*/
#include "kernel/rtlil.h"
#include "kernel/yosys.h"
#include "kernel/celltypes.h"
#include "kernel/mem.h"
@ -40,9 +41,9 @@ struct CleanZeroWidthPass : public Pass {
void clean_case(RTLIL::CaseRule *cs)
{
std::vector<SigSig> new_actions;
std::vector<RTLIL::SyncAction> new_actions;
for (auto &action : cs->actions)
if (GetSize(action.first) != 0)
if (GetSize(action.lhs) != 0)
new_actions.push_back(action);
std::swap(new_actions, cs->actions);
for (auto sw : cs->switches)
@ -167,9 +168,9 @@ struct CleanZeroWidthPass : public Pass {
new_memwr_actions.push_back(memwr);
}
std::swap(new_memwr_actions, sync->mem_write_actions);
std::vector<SigSig> new_actions;
std::vector<RTLIL::SyncAction> new_actions;
for (auto &action : sync->actions)
if (GetSize(action.first) != 0)
if (GetSize(action.lhs) != 0)
new_actions.push_back(action);
std::swap(new_actions, sync->actions);
}

9
passes/cmds/show.cc
View file

@ -17,6 +17,7 @@
*
*/
#include "kernel/rtlil.h"
#include "kernel/yosys.h"
#include "kernel/celltypes.h"
#include "kernel/log_help.h"
@ -370,12 +371,12 @@ struct ShowWorker
signals.insert(it);
}
void collect_proc_signals(std::vector<RTLIL::SigSig> &obj, std::set<RTLIL::SigSpec> &input_signals, std::set<RTLIL::SigSpec> &output_signals)
void collect_proc_signals(std::vector<RTLIL::SyncAction> &obj, std::set<RTLIL::SigSpec> &input_signals, std::set<RTLIL::SigSpec> &output_signals)
{
for (auto &it : obj) {
output_signals.insert(it.first);
if (!it.second.is_fully_const())
input_signals.insert(it.second);
output_signals.insert(it.lhs);
if (!it.rhs.is_fully_const())
input_signals.insert(it.rhs);
}
}