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rtlil: replace SigSig actions with new type SyncAction

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This commit is contained in:
Emil J. Tywoniak 2025-11-02 11:22:03 +01:00
parent 37875fdedf
commit 1eb696c786
19 changed files with 305 additions and 252 deletions
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17
backends/verilog/verilog_backend.cc
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@ -2122,13 +2122,14 @@ void dump_proc_switch(std::ostream &f, std::string indent, RTLIL::SwitchRule *sw
void dump_case_actions(std::ostream &f, std::string indent, RTLIL::CaseRule *cs)
{
for (auto it = cs->actions.begin(); it != cs->actions.end(); ++it) {
if (it->first.size() == 0)
if (it->lhs.size() == 0)
continue;
f << stringf("%s ", indent);
dump_sigspec(f, it->first);
dump_sigspec(f, it->lhs);
f << stringf(" = ");
dump_sigspec(f, it->second);
dump_sigspec(f, it->rhs);
f << stringf(";\n");
// TODO
}
}
@ -2259,7 +2260,7 @@ void case_body_find_regs(RTLIL::CaseRule *cs)
case_body_find_regs(*it2);
for (auto it = cs->actions.begin(); it != cs->actions.end(); ++it) {
for (auto &c : it->first.chunks())
for (auto &c : it->lhs.chunks())
if (c.wire != NULL)
reg_wires.insert(c.wire->name);
}
@ -2271,7 +2272,7 @@ void dump_process(std::ostream &f, std::string indent, RTLIL::Process *proc, boo
case_body_find_regs(&proc->root_case);
for (auto it = proc->syncs.begin(); it != proc->syncs.end(); ++it)
for (auto it2 = (*it)->actions.begin(); it2 != (*it)->actions.end(); it2++) {
for (auto &c : it2->first.chunks())
for (auto &c : it2->lhs.chunks())
if (c.wire != NULL)
reg_wires.insert(c.wire->name);
}
@ -2328,12 +2329,12 @@ void dump_process(std::ostream &f, std::string indent, RTLIL::Process *proc, boo
}
for (auto it = sync->actions.begin(); it != sync->actions.end(); ++it) {
if (it->first.size() == 0)
if (it->lhs.size() == 0)
continue;
f << stringf("%s ", indent);
dump_sigspec(f, it->first);
dump_sigspec(f, it->lhs);
f << stringf(" <= ");
dump_sigspec(f, it->second);
dump_sigspec(f, it->rhs);
f << stringf(";\n");
}