mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-11-05 13:56:04 +00:00
Code Activity

rtlil: replace SigSig actions with new type SyncAction

Browse source
This commit is contained in:
Emil J. Tywoniak 2025-11-02 11:22:03 +01:00
parent 37875fdedf
commit 1eb696c786
19 changed files with 305 additions and 252 deletions
Download patch file Download diff file Expand all files Collapse all files

16
backends/cxxrtl/cxxrtl_backend.cc
View file

@ -494,8 +494,8 @@ struct FlowGraph {
void add_case_rule_defs_uses(Node *node, const RTLIL::CaseRule *case_)
{
for (auto &action : case_->actions) {
add_defs(node, action.first, /*is_ff=*/false, /*inlinable=*/false);
add_uses(node, action.second);
add_defs(node, action.lhs, /*is_ff=*/false, /*inlinable=*/false);
add_uses(node, action.rhs);
}
for (auto sub_switch : case_->switches) {
add_uses(node, sub_switch->signal);
@ -512,10 +512,10 @@ struct FlowGraph {
for (auto sync : process->syncs) {
for (auto &action : sync->actions) {
if (sync->type == RTLIL::STp || sync->type == RTLIL::STn || sync->type == RTLIL::STe)
add_defs(node, action.first, /*is_ff=*/true, /*inlinable=*/false);
add_defs(node, action.lhs, /*is_ff=*/true, /*inlinable=*/false);
else
add_defs(node, action.first, /*is_ff=*/false, /*inlinable=*/false);
add_uses(node, action.second);
add_defs(node, action.lhs, /*is_ff=*/false, /*inlinable=*/false);
add_uses(node, action.rhs);
}
for (auto &memwr : sync->mem_write_actions) {
add_uses(node, memwr.address);
@ -1623,12 +1623,12 @@ struct CxxrtlWorker {
collect_sigspec_rhs(port.second, for_debug, cells);
}
void dump_assign(const RTLIL::SigSig &sigsig, bool for_debug = false)
void dump_assign(const RTLIL::SyncAction &action, bool for_debug = false)
{
f << indent;
dump_sigspec_lhs(sigsig.first, for_debug);
dump_sigspec_lhs(action.lhs, for_debug);
f << " = ";
dump_sigspec_rhs(sigsig.second, for_debug);
dump_sigspec_rhs(action.rhs, for_debug);
f << ";\n";
}

9
backends/rtlil/rtlil_backend.cc
View file

@ -189,7 +189,7 @@ void RTLIL_BACKEND::dump_cell(std::ostream &f, std::string indent, const RTLIL::
void RTLIL_BACKEND::dump_proc_case_body(std::ostream &f, std::string indent, const RTLIL::CaseRule *cs)
{
for (const auto& [lhs, rhs] : cs->actions) {
for (const auto& [lhs, rhs, _] : cs->actions) {
f << stringf("%s" "assign ", indent);
dump_sigspec(f, lhs);
f << stringf(" ");
@ -243,7 +243,7 @@ void RTLIL_BACKEND::dump_proc_sync(std::ostream &f, std::string indent, const RT
case RTLIL::STi: f << stringf("init\n"); break;
}
for (const auto& [lhs, rhs] : sy->actions) {
for (const auto& [lhs, rhs, _] : sy->actions) {
f << stringf("%s update ", indent);
dump_sigspec(f, lhs);
f << stringf(" ");
@ -375,8 +375,11 @@ void RTLIL_BACKEND::dump_design(std::ostream &f, RTLIL::Design *design, bool onl
for (auto* module : design->modules()) {
if (design->selected_whole_module(module->name))
flag_m = true;
if (design->selected(module))
if (design->selected(module)) {
count_selected_mods++;
if (module->has_processes())
log_warning("Module %s contains processes. Case action sources attributes will be lost.\n", log_id(module));
}
}
if (count_selected_mods > 1)
flag_m = true;

17
backends/verilog/verilog_backend.cc
View file

@ -2122,13 +2122,14 @@ void dump_proc_switch(std::ostream &f, std::string indent, RTLIL::SwitchRule *sw
void dump_case_actions(std::ostream &f, std::string indent, RTLIL::CaseRule *cs)
{
for (auto it = cs->actions.begin(); it != cs->actions.end(); ++it) {
if (it->first.size() == 0)
if (it->lhs.size() == 0)
continue;
f << stringf("%s ", indent);
dump_sigspec(f, it->first);
dump_sigspec(f, it->lhs);
f << stringf(" = ");
dump_sigspec(f, it->second);
dump_sigspec(f, it->rhs);
f << stringf(";\n");
// TODO
}
}
@ -2259,7 +2260,7 @@ void case_body_find_regs(RTLIL::CaseRule *cs)
case_body_find_regs(*it2);
for (auto it = cs->actions.begin(); it != cs->actions.end(); ++it) {
for (auto &c : it->first.chunks())
for (auto &c : it->lhs.chunks())
if (c.wire != NULL)
reg_wires.insert(c.wire->name);
}
@ -2271,7 +2272,7 @@ void dump_process(std::ostream &f, std::string indent, RTLIL::Process *proc, boo
case_body_find_regs(&proc->root_case);
for (auto it = proc->syncs.begin(); it != proc->syncs.end(); ++it)
for (auto it2 = (*it)->actions.begin(); it2 != (*it)->actions.end(); it2++) {
for (auto &c : it2->first.chunks())
for (auto &c : it2->lhs.chunks())
if (c.wire != NULL)
reg_wires.insert(c.wire->name);
}
@ -2328,12 +2329,12 @@ void dump_process(std::ostream &f, std::string indent, RTLIL::Process *proc, boo
}
for (auto it = sync->actions.begin(); it != sync->actions.end(); ++it) {
if (it->first.size() == 0)
if (it->lhs.size() == 0)
continue;
f << stringf("%s ", indent);
dump_sigspec(f, it->first);
dump_sigspec(f, it->lhs);
f << stringf(" <= ");
dump_sigspec(f, it->second);
dump_sigspec(f, it->rhs);
f << stringf(";\n");
}