diff --git a/techlibs/coolrunner2/cells_sim.v b/techlibs/coolrunner2/cells_sim.v
index 474d35a9a..52326fbb3 100644
--- a/techlibs/coolrunner2/cells_sim.v
+++ b/techlibs/coolrunner2/cells_sim.v
@@ -43,7 +43,6 @@ module ORTERM(IN, OUT);
 endmodule
 
 module MACROCELL_XOR(IN_PTC, IN_ORTERM, OUT);
-    parameter INVERT_PTC = 0;
     parameter INVERT_OUT = 0;
 
     input IN_PTC;
@@ -53,5 +52,5 @@ module MACROCELL_XOR(IN_PTC, IN_ORTERM, OUT);
     wire xor_intermed;
 
     assign OUT = INVERT_OUT ? ~xor_intermed : xor_intermed;
-    assign xor_intermed = INVERT_PTC ? IN_ORTERM ^ ~IN_PTC : IN_ORTERM ^ IN_PTC;
+    assign xor_intermed = IN_ORTERM ^ IN_PTC;
 endmodule
diff --git a/techlibs/coolrunner2/coolrunner2_sop.cpp b/techlibs/coolrunner2/coolrunner2_sop.cpp
index ed11880d5..cc214cfd2 100644
--- a/techlibs/coolrunner2/coolrunner2_sop.cpp
+++ b/techlibs/coolrunner2/coolrunner2_sop.cpp
@@ -117,7 +117,6 @@ struct Coolrunner2SopPass : public Pass {
 					{
 						// If there is only one term, don't construct an OR cell. Directly construct the XOR gate
 						auto xor_cell = module->addCell(NEW_ID, "\\MACROCELL_XOR");
-						xor_cell->setParam("\\INVERT_PTC", 0);
 						xor_cell->setParam("\\INVERT_OUT", has_invert);
 						xor_cell->setPort("\\IN_PTC", *intermed_wires.begin());
 						xor_cell->setPort("\\OUT", sop_output);
@@ -135,7 +134,6 @@ struct Coolrunner2SopPass : public Pass {
 
 						// Construct the XOR cell
 						auto xor_cell = module->addCell(NEW_ID, "\\MACROCELL_XOR");
-						xor_cell->setParam("\\INVERT_PTC", 0);
 						xor_cell->setParam("\\INVERT_OUT", has_invert);
 						xor_cell->setPort("\\IN_ORTERM", or_to_xor_wire);
 						xor_cell->setPort("\\OUT", sop_output);