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Improve VerificImporter support for writes to asymmetric memories

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Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf 2019-01-02 15:33:43 +01:00
parent 50b09de033
commit 1eb101a38a
1 changed files with 33 additions and 20 deletions
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27
frontends/verific/verific.cc
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@ -1200,13 +1200,19 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se
if (inst->Type() == OPER_WRITE_PORT || inst->Type() == OPER_CLOCKED_WRITE_PORT) if (inst->Type() == OPER_WRITE_PORT || inst->Type() == OPER_CLOCKED_WRITE_PORT)
{ {
RTLIL::Memory *memory = module->memories.at(RTLIL::escape_id(inst->GetOutput()->Name())); RTLIL::Memory *memory = module->memories.at(RTLIL::escape_id(inst->GetOutput()->Name()));
if (memory->width != int(inst->Input2Size())) int numchunks = int(inst->Input2Size()) / memory->width;
int chunksbits = ceil_log2(numchunks);
if ((numchunks * memory->width) != int(inst->Input2Size()) || (numchunks & (numchunks - 1)) != 0)
log_error("Import of asymmetric memories of this type is not supported yet: %s %s\n", inst->Name(), inst->GetOutput()->Name()); log_error("Import of asymmetric memories of this type is not supported yet: %s %s\n", inst->Name(), inst->GetOutput()->Name());
RTLIL::SigSpec addr = operatorInput1(inst); for (int i = 0; i < numchunks; i++)
RTLIL::SigSpec data = operatorInput2(inst); {
RTLIL::SigSpec addr = {operatorInput1(inst), RTLIL::Const(i, chunksbits)};
RTLIL::SigSpec data = operatorInput2(inst).extract(i * memory->width, memory->width);
RTLIL::Cell *cell = module->addCell(inst_name, "$memwr"); RTLIL::Cell *cell = module->addCell(numchunks == 1 ? inst_name :
RTLIL::IdString(stringf("%s_%d", inst_name.c_str(), i)), "$memwr");
cell->parameters["\\MEMID"] = memory->name.str(); cell->parameters["\\MEMID"] = memory->name.str();
cell->parameters["\\CLK_ENABLE"] = false; cell->parameters["\\CLK_ENABLE"] = false;
cell->parameters["\\CLK_POLARITY"] = true; cell->parameters["\\CLK_POLARITY"] = true;
@ -1222,6 +1228,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se
cell->parameters["\\CLK_ENABLE"] = true; cell->parameters["\\CLK_ENABLE"] = true;
cell->setPort("\\CLK", net_map_at(inst->GetClock())); cell->setPort("\\CLK", net_map_at(inst->GetClock()));
} }
}
continue; continue;
} }
@ -1893,13 +1900,19 @@ struct VerificPass : public Pass {
{ {
Message::SetConsoleOutput(0); Message::SetConsoleOutput(0);
Message::RegisterCallBackMsg(msg_func); Message::RegisterCallBackMsg(msg_func);
RuntimeFlags::SetVar("db_preserve_user_nets", 1); RuntimeFlags::SetVar("db_preserve_user_nets", 1);
RuntimeFlags::SetVar("db_allow_external_nets", 1); RuntimeFlags::SetVar("db_allow_external_nets", 1);
RuntimeFlags::SetVar("vhdl_support_variable_slice", 1); RuntimeFlags::SetVar("db_infer_wide_operators", 1);
RuntimeFlags::SetVar("vhdl_ignore_assertion_statements", 0);
RuntimeFlags::SetVar("veri_extract_dualport_rams", 0); RuntimeFlags::SetVar("veri_extract_dualport_rams", 0);
RuntimeFlags::SetVar("veri_extract_multiport_rams", 1); RuntimeFlags::SetVar("veri_extract_multiport_rams", 1);
RuntimeFlags::SetVar("db_infer_wide_operators", 1);
RuntimeFlags::SetVar("vhdl_extract_dualport_rams", 0);
RuntimeFlags::SetVar("vhdl_extract_multiport_rams", 1);
RuntimeFlags::SetVar("vhdl_support_variable_slice", 1);
RuntimeFlags::SetVar("vhdl_ignore_assertion_statements", 0);
// Workaround for VIPER #13851 // Workaround for VIPER #13851
RuntimeFlags::SetVar("veri_create_name_for_unnamed_gen_block", 1); RuntimeFlags::SetVar("veri_create_name_for_unnamed_gen_block", 1);