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https://github.com/YosysHQ/yosys
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Improved proc_mux performance for huge always blocks
This commit is contained in:
Clifford Wolf
parent
33a5b28e25
commit
1ea6db3db8
1 changed files with 155 additions and 38 deletions
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@ -27,35 +27,121 @@
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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RTLIL::SigSpec find_any_lvalue(const RTLIL::CaseRule *cs)
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struct SigSnippets
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{
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for (auto &action : cs->actions) {
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if (action.first.size())
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return action.first;
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}
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idict<SigSpec> sigidx;
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dict<SigBit, int> bit2snippet;
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pool<int> snippets;
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for (auto sw : cs->switches)
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for (auto cs2 : sw->cases) {
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RTLIL::SigSpec sig = find_any_lvalue(cs2);
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if (sig.size())
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return sig;
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}
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return RTLIL::SigSpec();
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}
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void extract_core_signal(const RTLIL::CaseRule *cs, RTLIL::SigSpec &sig)
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void insert(SigSpec sig)
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{
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for (auto &action : cs->actions) {
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RTLIL::SigSpec lvalue = action.first.extract(sig);
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if (lvalue.size())
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sig = lvalue;
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if (sig.empty())
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return;
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int key = sigidx(sig);
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if (snippets.count(key))
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return;
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SigSpec new_sig;
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for (int i = 0; i < GetSize(sig); i++)
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{
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int other_key = bit2snippet.at(sig[i], -1);
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if (other_key < 0) {
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new_sig.append(sig[i]);
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continue;
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}
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if (!new_sig.empty()) {
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int new_key = sigidx(new_sig);
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snippets.insert(new_key);
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for (auto bit : new_sig)
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bit2snippet[bit] = new_key;
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new_sig = SigSpec();
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}
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SigSpec other_sig = sigidx[other_key];
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int k = 0, n = 1;
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while (other_sig[k] != sig[i]) {
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k++;
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log_assert(k < GetSize(other_sig));
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}
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while (i+n < GetSize(sig) && k+n < GetSize(other_sig) && sig[i+n] == other_sig[k+n])
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n++;
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SigSpec sig1 = other_sig.extract(0, k);
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SigSpec sig2 = other_sig.extract(k, n);
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SigSpec sig3 = other_sig.extract(k+n, GetSize(other_sig)-k-n);
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for (auto bit : other_sig)
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bit2snippet.erase(bit);
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snippets.erase(other_key);
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insert(sig1);
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insert(sig2);
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insert(sig3);
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i += n-1;
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}
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if (!new_sig.empty()) {
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int new_key = sigidx(new_sig);
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snippets.insert(new_key);
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for (auto bit : new_sig)
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bit2snippet[bit] = new_key;
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}
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}
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void insert(const RTLIL::CaseRule *cs)
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{
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for (auto &action : cs->actions)
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insert(action.first);
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for (auto sw : cs->switches)
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for (auto cs2 : sw->cases)
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extract_core_signal(cs2, sig);
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insert(cs2);
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}
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};
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struct SnippetSwCache
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{
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dict<RTLIL::SwitchRule*, pool<int>, hash_ptr_ops> cache;
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const SigSnippets *snippets;
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int current_snippet;
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bool check(RTLIL::SwitchRule *sw)
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{
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return cache[sw].count(current_snippet) != 0;
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}
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void insert(const RTLIL::CaseRule *cs, vector<RTLIL::SwitchRule*> &sw_stack)
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{
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for (auto &action : cs->actions)
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for (auto bit : action.first) {
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int sn = snippets->bit2snippet.at(bit, -1);
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if (sn < 0)
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continue;
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for (auto sw : sw_stack)
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cache[sw].insert(sn);
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}
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for (auto sw : cs->switches) {
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sw_stack.push_back(sw);
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for (auto cs2 : sw->cases)
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insert(cs2, sw_stack);
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sw_stack.pop_back();
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}
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}
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void insert(const RTLIL::CaseRule *cs)
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{
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vector<RTLIL::SwitchRule*> sw_stack;
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insert(cs, sw_stack);
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}
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};
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RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const std::vector<RTLIL::SigSpec> &compare, RTLIL::SwitchRule *sw)
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{
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@ -179,7 +265,8 @@ void append_pmux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const std::ve
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last_mux_cell->parameters["\\S_WIDTH"] = last_mux_cell->getPort("\\S").size();
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}
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RTLIL::SigSpec signal_to_mux_tree(RTLIL::Module *mod, RTLIL::CaseRule *cs, const RTLIL::SigSpec &sig, const RTLIL::SigSpec &defval)
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RTLIL::SigSpec signal_to_mux_tree(RTLIL::Module *mod, SnippetSwCache &swcache, dict<RTLIL::SwitchRule*, bool, hash_ptr_ops> &swpara,
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RTLIL::CaseRule *cs, const RTLIL::SigSpec &sig, const RTLIL::SigSpec &defval)
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{
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RTLIL::SigSpec result = defval;
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@ -190,9 +277,37 @@ RTLIL::SigSpec signal_to_mux_tree(RTLIL::Module *mod, RTLIL::CaseRule *cs, const
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for (auto sw : cs->switches)
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{
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if (!swcache.check(sw))
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continue;
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// detect groups of parallel cases
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std::vector<int> pgroups(sw->cases.size());
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bool is_simple_parallel_case = true;
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if (!sw->get_bool_attribute("\\parallel_case")) {
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if (!swpara.count(sw)) {
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pool<Const> case_values;
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for (size_t i = 0; i < sw->cases.size(); i++) {
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RTLIL::CaseRule *cs2 = sw->cases[i];
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for (auto pat : cs2->compare) {
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if (!pat.is_fully_def())
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goto not_simple_parallel_case;
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Const cpat = pat.as_const();
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if (case_values.count(cpat))
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goto not_simple_parallel_case;
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case_values.insert(cpat);
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}
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}
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if (0)
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not_simple_parallel_case:
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is_simple_parallel_case = false;
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swpara[sw] = is_simple_parallel_case;
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} else {
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is_simple_parallel_case = swpara.at(sw);
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}
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}
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if (!is_simple_parallel_case) {
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BitPatternPool pool(sw->signal.size());
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bool extra_group_for_next_case = false;
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for (size_t i = 0; i < sw->cases.size(); i++) {
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@ -225,7 +340,7 @@ RTLIL::SigSpec signal_to_mux_tree(RTLIL::Module *mod, RTLIL::CaseRule *cs, const
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for (size_t i = 0; i < sw->cases.size(); i++) {
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int case_idx = sw->cases.size() - i - 1;
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RTLIL::CaseRule *cs2 = sw->cases[case_idx];
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RTLIL::SigSpec value = signal_to_mux_tree(mod, cs2, sig, initial_val);
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RTLIL::SigSpec value = signal_to_mux_tree(mod, swcache, swpara, cs2, sig, initial_val);
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if (last_mux_cell && pgroups[case_idx] == pgroups[case_idx+1])
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append_pmux(mod, sw->signal, cs2->compare, value, last_mux_cell, sw);
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else
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@ -238,24 +353,26 @@ RTLIL::SigSpec signal_to_mux_tree(RTLIL::Module *mod, RTLIL::CaseRule *cs, const
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void proc_mux(RTLIL::Module *mod, RTLIL::Process *proc)
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{
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bool first = true;
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while (1)
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{
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RTLIL::SigSpec sig = find_any_lvalue(&proc->root_case);
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if (sig.size() == 0)
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break;
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if (first) {
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log("Creating decoders for process `%s.%s'.\n", mod->name.c_str(), proc->name.c_str());
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first = false;
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}
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extract_core_signal(&proc->root_case, sig);
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SigSnippets sigsnip;
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sigsnip.insert(&proc->root_case);
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log(" creating decoder for signal `%s'.\n", log_signal(sig));
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SnippetSwCache swcache;
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swcache.snippets = &sigsnip;
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swcache.insert(&proc->root_case);
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RTLIL::SigSpec value = signal_to_mux_tree(mod, &proc->root_case, sig, RTLIL::SigSpec(RTLIL::State::Sx, sig.size()));
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dict<RTLIL::SwitchRule*, bool, hash_ptr_ops> swpara;
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int cnt = 0;
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for (int idx : sigsnip.snippets)
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{
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swcache.current_snippet = idx;
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RTLIL::SigSpec sig = sigsnip.sigidx[idx];
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log("%6d/%d: %s\n", ++cnt, GetSize(sigsnip.snippets), log_signal(sig));
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RTLIL::SigSpec value = signal_to_mux_tree(mod, swcache, swpara, &proc->root_case, sig, RTLIL::SigSpec(RTLIL::State::Sx, sig.size()));
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mod->connect(RTLIL::SigSig(sig, value));
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}
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}
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