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Merge remote-tracking branch 'origin/master' into xaig_dff
This commit is contained in:
Eddie Hung
commit
1ea1e8e54f
11 changed files with 339 additions and 216 deletions
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@ -227,6 +227,14 @@ module MUXCY(output O, input CI, DI, S);
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assign O = S ? CI : DI;
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endmodule
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module MUXF5(output O, input I0, I1, S);
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assign O = S ? I1 : I0;
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endmodule
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module MUXF6(output O, input I0, I1, S);
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assign O = S ? I1 : I0;
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endmodule
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(* abc9_box_id = 1, lib_whitebox *)
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module MUXF7(output O, input I0, I1, S);
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assign O = S ? I1 : I0;
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@ -237,6 +245,10 @@ module MUXF8(output O, input I0, I1, S);
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assign O = S ? I1 : I0;
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endmodule
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module MUXF9(output O, input I0, I1, S);
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assign O = S ? I1 : I0;
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endmodule
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module XORCY(output O, input CI, LI);
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assign O = CI ^ LI;
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endmodule
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@ -258,6 +270,26 @@ module CARRY4(
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assign CO[3] = S[3] ? CO[2] : DI[3];
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endmodule
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module CARRY8(
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output [7:0] CO,
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output [7:0] O,
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input CI,
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input CI_TOP,
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input [7:0] DI, S
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);
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parameter CARRY_TYPE = "SINGLE_CY8";
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wire CI4 = (CARRY_TYPE == "DUAL_CY4" ? CI_TOP : CO[3]);
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assign O = S ^ {CO[6:4], CI4, CO[2:0], CI};
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assign CO[0] = S[0] ? CI : DI[0];
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assign CO[1] = S[1] ? CO[0] : DI[1];
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assign CO[2] = S[2] ? CO[1] : DI[2];
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assign CO[3] = S[3] ? CO[2] : DI[3];
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assign CO[4] = S[4] ? CI4 : DI[4];
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assign CO[5] = S[5] ? CO[4] : DI[5];
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assign CO[6] = S[6] ? CO[5] : DI[6];
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assign CO[7] = S[7] ? CO[6] : DI[7];
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endmodule
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`ifdef _EXPLICIT_CARRY
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module CARRY0(output CO_CHAIN, CO_FABRIC, O, input CI, CI_INIT, DI, S);
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@ -281,6 +313,16 @@ endmodule
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`endif
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module ORCY (output O, input CI, I);
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assign O = CI | I;
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endmodule
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module MULT_AND (output LO, input I0, I1);
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assign LO = I0 & I1;
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endmodule
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// Flip-flops and latches.
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// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf#L238-L250
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(* abc9_box_id=1100, lib_whitebox, abc9_flop *)
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@ -394,6 +436,51 @@ module FDCE_1 (
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always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else if (CE) Q <= D;
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endmodule
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module FDCPE (
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output wire Q,
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(* clkbuf_sink *)
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(* invertible_pin = "IS_C_INVERTED" *)
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input C,
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input CE,
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(* invertible_pin = "IS_CLR_INVERTED" *)
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input CLR,
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input D,
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(* invertible_pin = "IS_PRE_INVERTED" *)
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input PRE
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);
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parameter [0:0] INIT = 1'b0;
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parameter [0:0] IS_C_INVERTED = 1'b0;
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parameter [0:0] IS_CLR_INVERTED = 1'b0;
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parameter [0:0] IS_PRE_INVERTED = 1'b0;
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wire c = C ^ IS_C_INVERTED;
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wire clr = CLR ^ IS_CLR_INVERTED;
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wire pre = PRE ^ IS_PRE_INVERTED;
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// Hacky model to avoid simulation-synthesis mismatches.
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reg qc, qp, qs;
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initial qc = INIT;
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initial qp = INIT;
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initial qs = 0;
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always @(posedge c, posedge clr) begin
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if (clr)
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qc <= 0;
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else if (CE)
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qc <= D;
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end
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always @(posedge c, posedge pre) begin
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if (pre)
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qp <= 1;
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else if (CE)
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qp <= D;
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end
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always @* begin
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if (clr)
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qs <= 0;
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else if (pre)
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qs <= 1;
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end
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assign Q = qs ? qp : qc;
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endmodule
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(* abc9_box_id=1104, lib_whitebox, abc9_flop *)
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module FDPE (
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(* abc9_arrival=303 *)
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@ -488,8 +575,8 @@ module LDCE (
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wire clr = CLR ^ IS_CLR_INVERTED;
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wire g = G ^ IS_G_INVERTED;
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always @*
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if (clr) Q = 1'b0;
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else if (GE && g) Q = D;
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if (clr) Q <= 1'b0;
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else if (GE && g) Q <= D;
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endmodule
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module LDPE (
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@ -510,8 +597,59 @@ module LDPE (
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wire g = G ^ IS_G_INVERTED;
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wire pre = PRE ^ IS_PRE_INVERTED;
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always @*
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if (pre) Q = 1'b1;
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else if (GE && g) Q = D;
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if (pre) Q <= 1'b1;
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else if (GE && g) Q <= D;
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endmodule
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module LDCPE (
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output reg Q,
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(* invertible_pin = "IS_CLR_INVERTED" *)
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input CLR,
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(* invertible_pin = "IS_D_INVERTED" *)
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input D,
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(* invertible_pin = "IS_G_INVERTED" *)
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input G,
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(* invertible_pin = "IS_GE_INVERTED" *)
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input GE,
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(* invertible_pin = "IS_PRE_INVERTED" *)
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input PRE
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);
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parameter [0:0] INIT = 1'b1;
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parameter [0:0] IS_CLR_INVERTED = 1'b0;
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parameter [0:0] IS_D_INVERTED = 1'b0;
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parameter [0:0] IS_G_INVERTED = 1'b0;
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parameter [0:0] IS_GE_INVERTED = 1'b0;
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parameter [0:0] IS_PRE_INVERTED = 1'b0;
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initial Q = INIT;
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wire d = D ^ IS_D_INVERTED;
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wire g = G ^ IS_G_INVERTED;
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wire ge = GE ^ IS_GE_INVERTED;
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wire clr = CLR ^ IS_CLR_INVERTED;
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wire pre = PRE ^ IS_PRE_INVERTED;
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always @*
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if (clr) Q <= 1'b0;
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else if (pre) Q <= 1'b1;
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else if (ge && g) Q <= d;
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endmodule
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module AND2B1L (
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output O,
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input DI,
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(* invertible_pin = "IS_SRI_INVERTED" *)
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input SRI
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);
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parameter [0:0] IS_SRI_INVERTED = 1'b0;
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assign O = DI & ~(SRI ^ IS_SRI_INVERTED);
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endmodule
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module OR2L (
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output O,
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input DI,
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(* invertible_pin = "IS_SRI_INVERTED" *)
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input SRI
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);
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parameter [0:0] IS_SRI_INVERTED = 1'b0;
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assign O = DI | (SRI ^ IS_SRI_INVERTED);
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endmodule
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// LUTRAM.
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@ -1377,6 +1515,20 @@ endmodule
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// Shift registers.
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module SRL16 (
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output Q,
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input A0, A1, A2, A3,
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(* clkbuf_sink *)
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input CLK,
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input D
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);
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parameter [15:0] INIT = 16'h0000;
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reg [15:0] r = INIT;
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assign Q = r[{A3,A2,A1,A0}];
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always @(posedge CLK) r <= { r[14:0], D };
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endmodule
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module SRL16E (
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// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904-L905
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(* abc9_arrival=1472 *)
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@ -1401,6 +1553,22 @@ module SRL16E (
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endgenerate
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endmodule
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module SRLC16 (
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output Q,
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output Q15,
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input A0, A1, A2, A3,
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(* clkbuf_sink *)
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input CLK,
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input D
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);
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parameter [15:0] INIT = 16'h0000;
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reg [15:0] r = INIT;
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assign Q15 = r[15];
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assign Q = r[{A3,A2,A1,A0}];
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always @(posedge CLK) r <= { r[14:0], D };
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endmodule
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module SRLC16E (
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output Q,
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output Q15,
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@ -1453,6 +1621,31 @@ module SRLC32E (
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endgenerate
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endmodule
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module CFGLUT5 (
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output CDO,
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output O5,
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output O6,
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input I4,
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input I3,
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input I2,
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input I1,
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input I0,
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input CDI,
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input CE,
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(* clkbuf_sink *)
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(* invertible_pin = "IS_CLK_INVERTED" *)
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input CLK
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);
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parameter [31:0] INIT = 32'h00000000;
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parameter [0:0] IS_CLK_INVERTED = 1'b0;
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wire clk = CLK ^ IS_CLK_INVERTED;
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reg [31:0] r = INIT;
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assign CDO = r[31];
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assign O5 = r[{1'b0, I3, I2, I1, I0}];
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assign O6 = r[{I4, I3, I2, I1, I0}];
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always @(posedge clk) if (CE) r <= {r[30:0], CDI};
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endmodule
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// DSP
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// Virtex 2, Virtex 2 Pro, Spartan 3.
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