quicklogic: Redo DSPv2 tests

tests/arch/quicklogic/dspv2/complex_mult.ys

@@ -1,23 +0,0 @@
-read_verilog <<EOF
-module top(input signed [16:0] ar, input signed [16:0] ai, input signed [16:0] br, input signed [16:0] bi, output reg signed [33:0] qr, output reg signed [33:0] qi, input clk);
-	reg signed [33:0] rr, ri, ir, ii;
-	always @(posedge clk) begin
-		rr <= ar * br;
-		ri <= ar * bi;
-		ir <= ai * br;
-		ii <= ai * bi;
-		qr <= rr - ii;
-		qi <= ir + ri;
-	end
-endmodule
-EOF
-
-synth_quicklogic -family qlf_k6n10f -dspv2 -run :coarse
-check -assert
-read_verilog +/quicklogic/qlf_k6n10f/dspv2_sim.v
-prep -top top -flatten
-opt_clean -purge
-opt -full
-opt_clean -purge
-check -assert
-dump

tests/arch/quicklogic/dspv2/run-test.sh

@@ -1,4 +0,0 @@
-#!/usr/bin/env bash
-set -eu
-source ../../../gen-tests-makefile.sh
-generate_mk --yosys-scripts --bash --yosys-args "-w 'Yosys has only limited support for tri-state logic at the moment.'"

tests/arch/quicklogic/dspv2/simple.ys

@@ -1,17 +0,0 @@
-read_verilog <<EOF
-module top(input [16:0] a, input [16:0] b, output reg [33:0] o, input clk, input [2:0] j);
-	reg [16:0] ar;
-	reg [16:0] br;
-
-	always @(posedge clk) begin
-		ar <= a;
-		br <= b;
-		o <= {ar * br, j};
-	end
-endmodule
-EOF
-
-synth_quicklogic -family qlf_k6n10f -dspv2 -run :coarse
-check
-opt_clean
-dump

tests/arch/quicklogic/dspv2/simple2.ys

@@ -1,12 +0,0 @@
-read_verilog <<EOF
-module top(input [16:0] a, input [16:0] b, input [16:0] c, input [16:0] d, output reg [33:0] o);
-	always @(*)
-		o <= (a * b) + (c * d);
-endmodule
-EOF
-
-synth_quicklogic -family qlf_k6n10f -dspv2 -run :coarse
-read_verilog +/quicklogic/qlf_k6n10f/dspv2_sim.v
-prep -top top -flatten
-opt_clean -purge
-dump

tests/arch/quicklogic/qlf_k6n10f/dspv2_full_dsp_flow.ys

@@ -0,0 +1,174 @@
+read_verilog <<EOF
+module top(input [6:0] a, input [4:0] b, input [4:0] c, input [4:0] d, input [4:0] e, input [4:0] f, output reg [7:0] o);
+	assign o = (a * b) + (c * d) + (e * f);
+endmodule
+EOF
+design -save gold
+
+synth_quicklogic -family qlf_k6n10f -dspv2 -run :coarse
+check -assert
+opt_clean
+select -assert-count 1 top/t:QL_DSPV2_MULT
+select -assert-count 2 top/t:QL_DSPV2_MULTADD
+read_verilog +/quicklogic/qlf_k6n10f/dspv2_sim.v
+prep -flatten -top top
+design -save gate
+
+design -reset
+design -copy-from gate -as gate top
+design -copy-from gold -as gold top
+async2sync
+equiv_make gold gate equiv
+opt -fast equiv
+equiv_induct equiv
+equiv_status -assert equiv
+
+design -reset
+read_verilog <<EOF
+module top(input signed [3:0] a, input signed [3:0] b, input signed [3:0] c, input signed [3:0] d, output signed [4:0] o);
+	assign o = (a * b) + (c * d);
+endmodule
+EOF
+design -save gold
+
+synth_quicklogic -family qlf_k6n10f -dspv2 -run :coarse
+check -assert
+opt_clean
+stat
+select -assert-count 1 top/t:QL_DSPV2_MULT
+select -assert-count 1 top/t:QL_DSPV2_MULTADD
+read_verilog +/quicklogic/qlf_k6n10f/dspv2_sim.v
+prep -flatten -top top
+design -save gate
+
+design -reset
+design -copy-from gate -as gate top
+design -copy-from gold -as gold top
+async2sync
+equiv_make gold gate equiv
+opt -fast equiv
+equiv_induct equiv
+equiv_status -assert equiv
+
+design -reset
+read_verilog <<EOF
+module top(input signed [16:0] ar, input signed [16:0] ai, input signed [16:0] br, input signed [16:0] bi, output reg signed [33:0] qr, output reg signed [33:0] qi, input clk);
+	reg signed [33:0] rr, ri, ir, ii;
+	always @(posedge clk) begin
+		rr <= ar * br;
+		ri <= ar * bi;
+		ir <= ai * br;
+		ii <= ai * bi;
+		qr <= rr - ii;
+		qi <= ir + ri;
+	end
+endmodule
+EOF
+
+synth_quicklogic -family qlf_k6n10f -dspv2 -run :coarse
+check -assert
+opt_clean
+select -assert-count 2 top/t:QL_DSPV2_MULT_REGOUT
+select -assert-count 2 top/t:QL_DSPV2_MULTADD_REGOUT
+
+design -reset
+read_verilog <<EOF
+module top(input signed [16:0] ar, input signed [16:0] ai, input signed [16:0] br, input signed [16:0] bi, output reg signed [33:0] qr, output reg signed [33:0] qi, input clk);
+	reg signed [16:0] ar_, ai_, br_, bi_;
+	always @(posedge clk) begin
+		ar_ <= ar;
+		ai_ <= ai;
+		br_ <= br;
+		bi_ <= bi;
+	end
+
+	reg signed [33:0] rr, ri, ir, ii;
+	always @(posedge clk) begin
+		rr <= ar_ * br_;
+		ri <= ar_ * bi_;
+		ir <= ai_ * br_;
+		ii <= ai_ * bi_;
+		qr <= rr - ii;
+		qi <= ir + ri;
+	end
+endmodule
+EOF
+
+synth_quicklogic -family qlf_k6n10f -dspv2 -run :coarse
+check -assert
+opt_clean -purge
+select -assert-count 2 top/t:QL_DSPV2_MULT_REGIN_REGOUT
+select -assert-count 2 top/t:QL_DSPV2_MULTADD_REGIN_REGOUT
+
+design -reset
+read_verilog <<EOF
+module top(input [6:0] a, input [4:0] b, input [4:0] c, input [4:0] d, output [7:0] e, output [7:0] f);
+	assign e = a * b;
+	assign f = c * d;
+endmodule
+EOF
+design -save gold
+
+synth_quicklogic -family qlf_k6n10f -dspv2 -run :coarse
+check -assert
+opt_clean
+select -assert-count 1 top/t:QL_DSPV2_MULT
+select -assert-count 1 top/c:*
+read_verilog +/quicklogic/qlf_k6n10f/dspv2_sim.v
+prep -flatten -top top
+design -save gate
+
+design -reset
+design -copy-from gate -as gate top
+design -copy-from gold -as gold top
+async2sync
+equiv_make gold gate equiv
+opt -fast equiv
+equiv_induct equiv
+equiv_status -assert equiv
+
+design -reset
+read_verilog <<EOF
+module top(input signed [6:0] a, input signed [4:0] b, input [4:0] c, input [4:0] d, output signed [7:0] e, output [7:0] f);
+	assign e = a * b;
+	assign f = c * d;
+endmodule
+EOF
+design -save gold
+
+synth_quicklogic -family qlf_k6n10f -dspv2 -run :coarse
+check -assert
+opt_clean
+select -assert-count 1 top/t:QL_DSPV2_MULT
+select -assert-count 1 top/c:*
+read_verilog +/quicklogic/qlf_k6n10f/dspv2_sim.v
+prep -flatten -top top
+design -save gate
+
+design -reset
+design -copy-from gate -as gate top
+design -copy-from gold -as gold top
+async2sync
+equiv_make gold gate equiv
+opt -fast equiv
+equiv_induct equiv
+equiv_status -assert equiv
+
+design -reset
+read_verilog <<EOF
+module top(input [16:0] a, input [16:0] b, output reg [33:0] o, input clk, input [2:0] j);
+	reg [16:0] ar;
+	reg [16:0] br;
+
+	always @(posedge clk) begin
+		ar <= a;
+		br <= b;
+		o <= {ar * br, j};
+	end
+endmodule
+EOF
+
+synth_quicklogic -family qlf_k6n10f -dspv2 -run :coarse
+check -assert
+opt_clean
+select -assert-count 1 top/t:QL_DSPV2_MULT_REGIN_REGOUT

tests/arch/quicklogic/qlf_k6n10f/dspv2_macc.tcl

@@ -0,0 +1,45 @@
+yosys -import
+
+proc testcase {top} {
+	log -header "Testcase $top"
+	log -push
+
+	design -load ast
+	prep -top $top
+	design -save gold
+
+	design -load ast
+	hierarchy -top $top
+	synth_quicklogic -family qlf_k6n10f -dspv2 -run :coarse
+	opt_clean
+	select -assert-none t:\$mul
+	stat
+	dump $top
+	select -assert-count 1 t:QL_DSPV2_MULTACC
+	read_verilog +/quicklogic/qlf_k6n10f/dspv2_sim.v
+	prep -flatten -top $top
+	design -save gate
+
+	design -clear
+	design -copy-from gate -as gate A:top
+	design -copy-from gold -as gold A:top
+	async2sync
+	equiv_make gold gate equiv
+	opt -fast equiv
+	equiv_induct equiv
+	equiv_status -assert equiv
+
+	log -pop
+}
+
+read_verilog dspv2_macc.v
+design -save ast
+
+testcase "macc_simple"
+testcase "macc_simple_clr"
+testcase "macc_simple_arst"
+testcase "macc_simple_ena"
+testcase "macc_simple_arst_clr_ena"
+testcase "macc_simple_preacc_clr"
+testcase "macc_simple_signed"
+testcase "macc_simple_signed_subtract"

tests/arch/quicklogic/qlf_k6n10f/dspv2_macc.v

@@ -0,0 +1,145 @@
+// Copyright 2020-2022 F4PGA Authors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+
+module macc_simple (
+    input  wire       clk,
+    input  wire [5:0] A,
+    input  wire [5:0] B,
+    output reg  [8:0] Z
+);
+
+    always @(posedge clk)
+        Z <= Z + (A * B);
+
+endmodule
+
+module macc_simple_clr (
+    input  wire       clk,
+    input  wire       clr,
+    input  wire [5:0] A,
+    input  wire [5:0] B,
+    output reg  [6:0] Z
+);
+
+    always @(posedge clk)
+        if (clr) Z <=     (A * B);
+        else     Z <= Z + (A * B);
+
+endmodule
+
+module macc_simple_arst (
+    input  wire       clk,
+    input  wire       rst,
+    input  wire [5:0] A,
+    input  wire [5:0] B,
+    output reg  [8:0] Z
+);
+
+    always @(posedge clk or posedge rst)
+        if (rst) Z <= 0;
+        else     Z <= Z + (A * B);
+
+endmodule
+
+module macc_simple_ena (
+    input  wire       clk,
+    input  wire       ena,
+    input  wire [5:0] A,
+    input  wire [5:0] B,
+    output reg  [8:0] Z
+);
+
+    always @(posedge clk)
+        if (ena) Z <= Z + (A * B);
+
+endmodule
+
+module macc_simple_arst_clr_ena (
+    input  wire       clk,
+    input  wire       rst,
+    input  wire       clr,
+    input  wire       ena,
+    input  wire [5:0] A,
+    input  wire [5:0] B,
+    output reg  [7:0] Z
+);
+
+    always @(posedge clk or posedge rst)
+        if (rst)     Z <= 0;
+        else if (ena) begin
+            if (clr) Z <=     (A * B);
+            else     Z <= Z + (A * B);
+        end
+
+endmodule
+
+module macc_simple_preacc (
+    input  wire       clk,
+    input  wire [4:0] A,
+    input  wire [4:0] B,
+    output wire [7:0] Z
+);
+
+    reg [7:0] acc;
+
+    assign Z = acc + (A * B);
+
+    always @(posedge clk)
+        acc <= Z;
+
+endmodule
+
+module macc_simple_preacc_clr (
+    input  wire       clk,
+    input  wire       clr,
+    input  wire [5:0] A,
+    input  wire [5:0] B,
+    output reg  [7:0] Z
+);
+
+    reg [7:0] acc;
+
+    assign Z = (clr) ? (A * B) : (acc + (A * B));
+
+    always @(posedge clk)
+        acc <= Z;
+
+endmodule
+
+module macc_simple_signed (
+    input  wire        clk,
+    input  wire signed [4:0] A,
+    input  wire signed [4:0] B,
+    output reg  signed [7:0] Z
+);
+
+    always @(posedge clk)
+        Z <= Z + (A * B);
+
+endmodule
+
+module macc_simple_signed_subtract (
+    input  wire        clk,
+    input  wire signed [4:0] A,
+    input  wire signed [4:0] B,
+    output reg  signed [7:0] Z
+);
+
+    always @(posedge clk)
+        Z <= Z - (A * B);
+
+endmodule
+