mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-08-06 03:10:26 +00:00
Code Activity

Added $assert cell

Browse source
This commit is contained in:
Clifford Wolf 2014-01-19 14:03:40 +01:00
parent 9a1eb45c75
commit 1e67099b77
7 changed files with 120 additions and 1 deletions
Download patch file Download diff file Expand all files Collapse all files

4
manual/CHAPTER_CellLib.tex
View file

@ -418,3 +418,7 @@ from the gate level logic network can be mapped to physical flip-flop cells from
pass. The combinatorial logic cells can be mapped to physical cells from a Liberty file via ABC \citeweblink{ABC}
using the {\tt abc} pass.
\begin{fixme}
Add information about {\tt \$assert} cells.
\end{fixme}