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https://github.com/YosysHQ/yosys
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Remove .c_str() from parameters to log_debug()
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parent
cb9d0b6ff9
commit
1e5f920dbd
17 changed files with 67 additions and 67 deletions
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@ -162,7 +162,7 @@ struct OptLutWorker
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{
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if (lut_width <= dlogic_conn.first)
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{
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log_debug(" LUT has illegal connection to %s cell %s.%s.\n", lut_dlogic.second->type.c_str(), log_id(module), log_id(lut_dlogic.second));
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log_debug(" LUT has illegal connection to %s cell %s.%s.\n", lut_dlogic.second->type, log_id(module), log_id(lut_dlogic.second));
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log_debug(" LUT input A[%d] not present.\n", dlogic_conn.first);
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legal = false;
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break;
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@ -173,8 +173,8 @@ struct OptLutWorker
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if (sigmap(lut_input[dlogic_conn.first]) != sigmap(lut_dlogic.second->getPort(dlogic_conn.second)[0]))
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{
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log_debug(" LUT has illegal connection to %s cell %s.%s.\n", lut_dlogic.second->type.c_str(), log_id(module), log_id(lut_dlogic.second));
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log_debug(" LUT input A[%d] (wire %s) not connected to %s port %s (wire %s).\n", dlogic_conn.first, log_signal(lut_input[dlogic_conn.first]), lut_dlogic.second->type.c_str(), dlogic_conn.second.c_str(), log_signal(lut_dlogic.second->getPort(dlogic_conn.second)));
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log_debug(" LUT has illegal connection to %s cell %s.%s.\n", lut_dlogic.second->type, log_id(module), log_id(lut_dlogic.second));
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log_debug(" LUT input A[%d] (wire %s) not connected to %s port %s (wire %s).\n", dlogic_conn.first, log_signal(lut_input[dlogic_conn.first]), lut_dlogic.second->type, dlogic_conn.second, log_signal(lut_dlogic.second->getPort(dlogic_conn.second)));
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legal = false;
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break;
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}
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@ -182,7 +182,7 @@ struct OptLutWorker
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if (legal)
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{
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log_debug(" LUT has legal connection to %s cell %s.%s.\n", lut_dlogic.second->type.c_str(), log_id(module), log_id(lut_dlogic.second));
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log_debug(" LUT has legal connection to %s cell %s.%s.\n", lut_dlogic.second->type, log_id(module), log_id(lut_dlogic.second));
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lut_legal_dlogics.insert(lut_dlogic);
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for (auto &dlogic_conn : dlogic_map)
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lut_dlogic_inputs.insert(dlogic_conn.first);
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@ -496,9 +496,9 @@ struct OptLutWorker
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lutM_new_table.set(eval, (RTLIL::State) evaluate_lut(lutB, eval_inputs));
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}
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log_debug(" Cell A truth table: %s.\n", lutA->getParam(ID::LUT).as_string().c_str());
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log_debug(" Cell B truth table: %s.\n", lutB->getParam(ID::LUT).as_string().c_str());
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log_debug(" Merged truth table: %s.\n", lutM_new_table.as_string().c_str());
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log_debug(" Cell A truth table: %s.\n", lutA->getParam(ID::LUT).as_string());
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log_debug(" Cell B truth table: %s.\n", lutB->getParam(ID::LUT).as_string());
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log_debug(" Merged truth table: %s.\n", lutM_new_table.as_string());
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lutM->setParam(ID::LUT, lutM_new_table);
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lutM->setPort(ID::A, lutM_new_inputs);
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