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Remove .c_str() from parameters to log_debug()

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Robert O'Callahan 2025-09-22 22:04:17 +00:00 • committed by Robert O'Callahan
parent cb9d0b6ff9
commit 1e5f920dbd
17 changed files with 67 additions and 67 deletions
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8
passes/opt/opt_clean.cc
View file

@ -204,7 +204,7 @@ void rmunused_module_cells(Module *module, bool verbose)
for (auto cell : unused) {
if (verbose)
log_debug(" removing unused `%s' cell `%s'.\n", cell->type.c_str(), cell->name.c_str());
log_debug(" removing unused `%s' cell `%s'.\n", cell->type, cell->name);
module->design->scratchpad_set_bool("opt.did_something", true);
if (cell->is_builtin_ff())
ffinit.remove_init(cell->getPort(ID::Q));
@ -215,7 +215,7 @@ void rmunused_module_cells(Module *module, bool verbose)
for (auto it : mem_unused)
{
if (verbose)
log_debug(" removing unused memory `%s'.\n", it.c_str());
log_debug(" removing unused memory `%s'.\n", it);
delete module->memories.at(it);
module->memories.erase(it);
}
@ -496,7 +496,7 @@ bool rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbos
int del_temp_wires_count = 0;
for (auto wire : del_wires_queue) {
if (ys_debug() || (check_public_name(wire->name) && verbose))
log_debug(" removing unused non-port wire %s.\n", wire->name.c_str());
log_debug(" removing unused non-port wire %s.\n", wire->name);
else
del_temp_wires_count++;
}
@ -636,7 +636,7 @@ void rmunused_module(RTLIL::Module *module, bool purge_mode, bool verbose, bool
}
for (auto cell : delcells) {
if (verbose)
log_debug(" removing buffer cell `%s': %s = %s\n", cell->name.c_str(),
log_debug(" removing buffer cell `%s': %s = %s\n", cell->name,
log_signal(cell->getPort(ID::Y)), log_signal(cell->getPort(ID::A)));
module->remove(cell);
}

14
passes/opt/opt_lut.cc
View file

@ -162,7 +162,7 @@ struct OptLutWorker
{
if (lut_width <= dlogic_conn.first)
{
log_debug(" LUT has illegal connection to %s cell %s.%s.\n", lut_dlogic.second->type.c_str(), log_id(module), log_id(lut_dlogic.second));
log_debug(" LUT has illegal connection to %s cell %s.%s.\n", lut_dlogic.second->type, log_id(module), log_id(lut_dlogic.second));
log_debug(" LUT input A[%d] not present.\n", dlogic_conn.first);
legal = false;
break;
@ -173,8 +173,8 @@ struct OptLutWorker
if (sigmap(lut_input[dlogic_conn.first]) != sigmap(lut_dlogic.second->getPort(dlogic_conn.second)[0]))
{
log_debug(" LUT has illegal connection to %s cell %s.%s.\n", lut_dlogic.second->type.c_str(), log_id(module), log_id(lut_dlogic.second));
log_debug(" LUT input A[%d] (wire %s) not connected to %s port %s (wire %s).\n", dlogic_conn.first, log_signal(lut_input[dlogic_conn.first]), lut_dlogic.second->type.c_str(), dlogic_conn.second.c_str(), log_signal(lut_dlogic.second->getPort(dlogic_conn.second)));
log_debug(" LUT has illegal connection to %s cell %s.%s.\n", lut_dlogic.second->type, log_id(module), log_id(lut_dlogic.second));
log_debug(" LUT input A[%d] (wire %s) not connected to %s port %s (wire %s).\n", dlogic_conn.first, log_signal(lut_input[dlogic_conn.first]), lut_dlogic.second->type, dlogic_conn.second, log_signal(lut_dlogic.second->getPort(dlogic_conn.second)));
legal = false;
break;
}
@ -182,7 +182,7 @@ struct OptLutWorker
if (legal)
{
log_debug(" LUT has legal connection to %s cell %s.%s.\n", lut_dlogic.second->type.c_str(), log_id(module), log_id(lut_dlogic.second));
log_debug(" LUT has legal connection to %s cell %s.%s.\n", lut_dlogic.second->type, log_id(module), log_id(lut_dlogic.second));
lut_legal_dlogics.insert(lut_dlogic);
for (auto &dlogic_conn : dlogic_map)
lut_dlogic_inputs.insert(dlogic_conn.first);
@ -496,9 +496,9 @@ struct OptLutWorker
lutM_new_table.set(eval, (RTLIL::State) evaluate_lut(lutB, eval_inputs));
}
log_debug(" Cell A truth table: %s.\n", lutA->getParam(ID::LUT).as_string().c_str());
log_debug(" Cell B truth table: %s.\n", lutB->getParam(ID::LUT).as_string().c_str());
log_debug(" Merged truth table: %s.\n", lutM_new_table.as_string().c_str());
log_debug(" Cell A truth table: %s.\n", lutA->getParam(ID::LUT).as_string());
log_debug(" Cell B truth table: %s.\n", lutB->getParam(ID::LUT).as_string());
log_debug(" Merged truth table: %s.\n", lutM_new_table.as_string());
lutM->setParam(ID::LUT, lutM_new_table);
lutM->setPort(ID::A, lutM_new_inputs);

6
passes/opt/opt_merge.cc
View file

@ -300,11 +300,11 @@ struct OptMergeWorker
}
did_something = true;
log_debug(" Cell `%s' is identical to cell `%s'.\n", cell->name.c_str(), other_cell->name.c_str());
log_debug(" Cell `%s' is identical to cell `%s'.\n", cell->name, other_cell->name);
for (auto &it : cell->connections()) {
if (cell->output(it.first)) {
RTLIL::SigSpec other_sig = other_cell->getPort(it.first);
log_debug(" Redirecting output %s: %s = %s\n", it.first.c_str(),
log_debug(" Redirecting output %s: %s = %s\n", it.first,
log_signal(it.second), log_signal(other_sig));
Const init = initvals(other_sig);
initvals.remove_init(it.second);
@ -314,7 +314,7 @@ struct OptMergeWorker
initvals.set_init(other_sig, init);
}
}
log_debug(" Removing %s cell `%s' from module `%s'.\n", cell->type.c_str(), cell->name.c_str(), module->name.c_str());
log_debug(" Removing %s cell `%s' from module `%s'.\n", cell->type, cell->name, module->name);
module->remove(cell);
total_count++;
}