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https://github.com/YosysHQ/yosys
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Remove .c_str() from parameters to log_debug()
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cb9d0b6ff9
commit
1e5f920dbd
17 changed files with 67 additions and 67 deletions
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@ -143,14 +143,14 @@ unsigned int CellCosts::get(RTLIL::Cell *cell)
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return 1;
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if (design_ && design_->module(cell->type) && cell->parameters.empty()) {
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log_debug("%s is a module, recurse\n", cell->name.c_str());
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log_debug("%s is a module, recurse\n", cell->name);
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return get(design_->module(cell->type));
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} else if (cell->is_builtin_ff()) {
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log_assert(cell->hasPort(ID::Q) && "Weird flip flop");
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log_debug("%s is ff\n", cell->name.c_str());
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log_debug("%s is ff\n", cell->name);
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return cell->getParam(ID::WIDTH).as_int();
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} else if (cell->type.in(ID($mem), ID($mem_v2))) {
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log_debug("%s is mem\n", cell->name.c_str());
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log_debug("%s is mem\n", cell->name);
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return cell->getParam(ID::WIDTH).as_int() * cell->getParam(ID::SIZE).as_int();
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} else if (y_coef(cell->type)) {
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// linear with Y_WIDTH or WIDTH
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@ -159,23 +159,23 @@ unsigned int CellCosts::get(RTLIL::Cell *cell)
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int width = cell->getParam(param).as_int();
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if (cell->type == ID($demux))
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width <<= cell->getParam(ID::S_WIDTH).as_int();
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log_debug("%s Y*coef %d * %d\n", cell->name.c_str(), width, y_coef(cell->type));
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log_debug("%s Y*coef %d * %d\n", cell->name, width, y_coef(cell->type));
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return width * y_coef(cell->type);
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} else if (sum_coef(cell->type)) {
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// linear with sum of port widths
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unsigned int sum = port_width_sum(cell);
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log_debug("%s sum*coef %d * %d\n", cell->name.c_str(), sum, sum_coef(cell->type));
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log_debug("%s sum*coef %d * %d\n", cell->name, sum, sum_coef(cell->type));
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return sum * sum_coef(cell->type);
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} else if (max_inp_coef(cell->type)) {
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// linear with largest input width
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unsigned int max = max_inp_width(cell);
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log_debug("%s max*coef %d * %d\n", cell->name.c_str(), max, max_inp_coef(cell->type));
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log_debug("%s max*coef %d * %d\n", cell->name, max, max_inp_coef(cell->type));
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return max * max_inp_coef(cell->type);
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} else if (is_div_mod(cell->type) || cell->type == ID($mul)) {
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// quadratic with sum of port widths
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unsigned int sum = port_width_sum(cell);
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unsigned int coef = cell->type == ID($mul) ? 3 : 5;
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log_debug("%s coef*(sum**2) %d * %d\n", cell->name.c_str(), coef, sum * sum);
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log_debug("%s coef*(sum**2) %d * %d\n", cell->name, coef, sum * sum);
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return coef * sum * sum;
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} else if (cell->type.in(ID($macc), ID($macc_v2))) {
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// quadratic per term
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@ -196,15 +196,15 @@ unsigned int CellCosts::get(RTLIL::Cell *cell)
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} else if (cell->type == ID($lut)) {
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int width = cell->getParam(ID::WIDTH).as_int();
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unsigned int cost = 1U << (unsigned int)width;
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log_debug("%s is 2**%d\n", cell->name.c_str(), width);
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log_debug("%s is 2**%d\n", cell->name, width);
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return cost;
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} else if (cell->type == ID($sop)) {
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int width = cell->getParam(ID::WIDTH).as_int();
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int depth = cell->getParam(ID::DEPTH).as_int();
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log_debug("%s is (2*%d + 1)*%d\n", cell->name.c_str(), width, depth);
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log_debug("%s is (2*%d + 1)*%d\n", cell->name, width, depth);
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return (2 * width + 1) * depth;
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} else if (is_free(cell->type)) {
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log_debug("%s is free\n", cell->name.c_str());
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log_debug("%s is free\n", cell->name);
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return 0;
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}
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// TODO: $fsm
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