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Removing typical phases doc

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Moved remaining content into relevant places.
Added `load_design.rst` to more scripting.
Split fsm handling and abc out of optimization passes. Also moved things around to match the general flow previously described.
Changed generic `synth` for `prep` instead.
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Krystine Sherwin 2023-12-07 17:14:21 +13:00
parent f9ce3d1c26
commit 1e3b90ae56
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31
docs/source/using_yosys/synthesis/synth.rst
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@ -1,15 +1,5 @@
Introduction to synthesis
-------------------------
The generic ``synth``
~~~~~~~~~~~~~~~~~~~~~
The following commands are executed by the :cmd:ref:`synth` command:
.. literalinclude:: /cmd/synth.rst
:start-at: begin:
:end-before: .. raw:: latex
:dedent:
Synth commands
--------------
Packaged ``synth_*`` commands
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
@ -38,3 +28,20 @@ being targeted.
- :doc:`/cmd/synth_quicklogic`
- :doc:`/cmd/synth_sf2`
- :doc:`/cmd/synth_xilinx`
General synthesis
~~~~~~~~~~~~~~~~~
In addition to the above hardware-specific synth commands, there is also
:doc:`/cmd/prep`. This command is limited to coarse-grain synthesis, without
getting into any architecture-specific mappings or optimizations. Among other
things, this is useful for design verification.
The following commands are executed by the :cmd:ref:`prep` command:
.. literalinclude:: /cmd/prep.rst
:start-at: begin:
:end-before: .. raw:: latex
:dedent:
The following sections will get more into what each of these commands do.