Removing typical phases doc

Moved remaining content into relevant places.
Added `load_design.rst` to more scripting.
Split fsm handling and abc out of optimization passes. Also moved things around to match the general flow previously described.
Changed generic `synth` for `prep` instead.

docs/source/using_yosys/more_scripting/index.rst

@@ -2,8 +2,9 @@ More scripting
 --------------
 
 .. toctree::
-	:maxdepth: 3
+   :maxdepth: 3
 
-	selections
-	interactive_investigation
-	troubleshooting
+   load_design
+   selections
+   interactive_investigation
+   troubleshooting

docs/source/using_yosys/more_scripting/load_design.rst

@@ -0,0 +1,37 @@
+Loading a design
+~~~~~~~~~~~~~~~~
+
+keyword: Frontends
+
+- :doc:`/cmd/read_verilog`
+
+.. todo:: include ``read_verilog <<EOF``, also other methods of loading designs
+
+.. code-block:: yoscrypt
+
+    read_verilog file1.v
+    read_verilog -I include_dir -D enable_foo -D WIDTH=12 file2.v
+    read_verilog -lib cell_library.v
+
+    verilog_defaults -add -I include_dir
+    read_verilog file3.v
+    read_verilog file4.v
+    verilog_defaults -clear
+
+    verilog_defaults -push
+    verilog_defaults -add -I include_dir
+    read_verilog file5.v
+    read_verilog file6.v
+    verilog_defaults -pop
+
+Others:
+
+- :doc:`/cmd/read`
+- `GHDL plugin`_ for VHDL
+- :doc:`/cmd/read_rtlil` (direct textual representation of Yosys internal state)
+- :doc:`/cmd/read_aiger`
+- :doc:`/cmd/read_blif`
+- :doc:`/cmd/read_json`
+- :doc:`/cmd/read_liberty`
+
+.. _GHDL plugin: https://github.com/ghdl/ghdl-yosys-plugin