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	Improvements and fixes in autotest.sh script and test_autotb
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					 2 changed files with 9 additions and 9 deletions
				
			
		|  | @ -73,8 +73,8 @@ static std::string idy(std::string str1, std::string str2 = std::string(), std:: | ||||||
| 
 | 
 | ||||||
| static void autotest(std::ostream &f, RTLIL::Design *design, int num_iter) | static void autotest(std::ostream &f, RTLIL::Design *design, int num_iter) | ||||||
| { | { | ||||||
| 	f << stringf("`ifndef dmp_name\n"); | 	f << stringf("`ifndef outfile\n"); | ||||||
| 	f << stringf("\t`define dmp_name \"not_defined.dmp\"\n"); | 	f << stringf("\t`define outfile \"/dev/stdout\"\n"); | ||||||
| 	f << stringf("`endif\n"); | 	f << stringf("`endif\n"); | ||||||
| 
 | 
 | ||||||
| 	f << stringf("module testbench;\n\n"); | 	f << stringf("module testbench;\n\n"); | ||||||
|  | @ -301,7 +301,7 @@ static void autotest(std::ostream &f, RTLIL::Design *design, int num_iter) | ||||||
| 	f << stringf("initial begin\n"); | 	f << stringf("initial begin\n"); | ||||||
| 	f << stringf("\t// $dumpfile(\"testbench.vcd\");\n"); | 	f << stringf("\t// $dumpfile(\"testbench.vcd\");\n"); | ||||||
| 	f << stringf("\t// $dumpvars(0, testbench);\n"); | 	f << stringf("\t// $dumpvars(0, testbench);\n"); | ||||||
| 	f << stringf("\tfile = $fopen(`dmp_name);\n"); | 	f << stringf("\tfile = $fopen(`outfile);\n"); | ||||||
| 	for (auto it = design->modules_.begin(); it != design->modules_.end(); ++it) | 	for (auto it = design->modules_.begin(); it != design->modules_.end(); ++it) | ||||||
| 		if (!it->second->get_bool_attribute("\\gentb_skip")) | 		if (!it->second->get_bool_attribute("\\gentb_skip")) | ||||||
| 			f << stringf("\t%s;\n", idy(it->first.str(), "test").c_str()); | 			f << stringf("\t%s;\n", idy(it->first.str(), "test").c_str()); | ||||||
|  |  | ||||||
|  | @ -65,18 +65,18 @@ compile_and_run() { | ||||||
| 	if $use_modelsim; then | 	if $use_modelsim; then | ||||||
| 		altver=$( ls -v /opt/altera/ | grep '^[0-9]' | tail -n1; ) | 		altver=$( ls -v /opt/altera/ | grep '^[0-9]' | tail -n1; ) | ||||||
| 		/opt/altera/$altver/modelsim_ase/bin/vlib work | 		/opt/altera/$altver/modelsim_ase/bin/vlib work | ||||||
| 		/opt/altera/$altver/modelsim_ase/bin/vlog +define+dmp_name=\"$output\" "$@" | 		/opt/altera/$altver/modelsim_ase/bin/vlog +define+outfile=\"$output\" "$@" | ||||||
| 		/opt/altera/$altver/modelsim_ase/bin/vsim -c -do 'run -all; exit;' testbench | 		/opt/altera/$altver/modelsim_ase/bin/vsim -c -do 'run -all; exit;' testbench | ||||||
| 	elif $use_xsim; then | 	elif $use_xsim; then | ||||||
| 		( | 		( | ||||||
| 			set +x | 			set +x | ||||||
| 			files=( "$@" ) | 			files=( "$@" ) | ||||||
| 			xilver=$( ls -v /opt/Xilinx/Vivado/ | grep '^[0-9]' | tail -n1; ) | 			xilver=$( ls -v /opt/Xilinx/Vivado/ | grep '^[0-9]' | tail -n1; ) | ||||||
| 			/opt/Xilinx/Vivado/$xilver/bin/xvlog "${files[@]}" | 			/opt/Xilinx/Vivado/$xilver/bin/xvlog -d outfile=\"$output\" "${files[@]}" | ||||||
| 			/opt/Xilinx/Vivado/$xilver/bin/xelab -R work.testbench | grep '#OUT#' > "$output" | 			/opt/Xilinx/Vivado/$xilver/bin/xelab -R work.testbench | ||||||
| 		) | 		) | ||||||
| 	else | 	else | ||||||
| 		iverilog  -Ddmp_name=\"$output\" -s testbench -o "$exe" "$@"  | 		iverilog -Doutfile=\"$output\" -s testbench -o "$exe" "$@" | ||||||
| 		vvp -n "$exe" | 		vvp -n "$exe" | ||||||
| 	fi | 	fi | ||||||
| } | } | ||||||
|  |  | ||||||
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