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Added GP_RINGOSC primitive

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Andrew Zonenberg 2016-04-06 22:40:25 -07:00
parent f6a0f2cf73
commit 1df559c706
1 changed files with 26 additions and 0 deletions
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26
techlibs/greenpak4/cells_sim.v
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@ -75,6 +75,9 @@ module GP_LFOSC(input PWRDN, output reg CLKOUT);
initial CLKOUT = 0; initial CLKOUT = 0;
//auto powerdown not implemented for simulation
//output dividers not implemented for simulation
always begin always begin
if(PWRDN) if(PWRDN)
clkout = 0; clkout = 0;
@ -87,6 +90,29 @@ module GP_LFOSC(input PWRDN, output reg CLKOUT);
endmodule endmodule
module GP_RINGOSC(input PWRDN, output reg CLKOUT);
parameter PWRDN_EN = 0;
parameter AUTO_PWRDN = 0;
parameter OUT_DIV = 1;
initial CLKOUT = 0;
//output dividers not implemented for simulation
//auto powerdown not implemented for simulation
always begin
if(PWRDN)
clkout = 0;
else begin
//half period of 27 MHz
#18.518;
clkout = ~clkout;
end
end
endmodule
module GP_COUNT8(input CLK, input wire RST, output reg OUT); module GP_COUNT8(input CLK, input wire RST, output reg OUT);
parameter RESET_MODE = "RISING"; parameter RESET_MODE = "RISING";