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ecp5: Adding DRAM map

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Signed-off-by: David Shah <davey1576@gmail.com>
This commit is contained in:
David Shah 2018-07-13 14:08:42 +02:00
parent b1b9e23f94
commit 1def34f2a6
3 changed files with 76 additions and 1 deletions
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37
techlibs/ecp5/cells_sim.v
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@ -52,7 +52,7 @@ module TRELLIS_RAM16X2 (
input RAD0, RAD1, RAD2, RAD3,
output DO0, DO1
);
parameter WCKMUX = "WCK";
parameter WCKMUX = "WCK";
parameter WREMUX = "WRE";
parameter INITVAL_0 = 16'h0000;
parameter INITVAL_1 = 16'h0000;
@ -87,6 +87,41 @@ endmodule
// ---------------------------------------
module TRELLIS_DPR16X4 (
input [3:0] DI,
input [3:0] WAD,
input WRE, WCK,
input [3:0] RAD,
output [3:0] DO
);
parameter WCKMUX = "WCK";
parameter WREMUX = "WRE";
parameter [63:0] INITVAL = 64'h0000000000000000;
reg [3:0] mem[15:0];
integer i;
initial begin
for (i = 0; i < 16; i = i + 1)
mem[i] <= INITVAL[4*i :+ 4];
end
wire muxwck = (WCKMUX == "INV") ? ~WCK : WCK;
wire muxwre = (WREMUX == "1") ? 1'b1 :
(WREMUX == "0") ? 1'b0 :
(WREMUX == "INV") ? ~WRE :
WRE;
always @(posedge muxwck)
if (muxwre)
mem[WAD] <= DI;
assign DO = mem[RAD];
endmodule
// ---------------------------------------
module DPR16X4C (
input [3:0] DI,
input WCK, WRE,