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Reduce comparisons of size_t and int

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`Const::size()` returns int, so change iterators that use it to `auto` instead of `size_t`.
For cases where size is being explicitly cast to `int`, use the wrapper that we already have instead: `Yosys::GetSize()`.
This commit is contained in:
Krystine Sherwin 2024-11-29 12:31:34 +13:00
parent 6f3376cbe6
commit 1de5d98ae2
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9 changed files with 59 additions and 59 deletions
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10
frontends/ast/ast.cc
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@ -931,7 +931,7 @@ bool AstNode::bits_only_01() const
RTLIL::Const AstNode::bitsAsUnsizedConst(int width)
{
RTLIL::State extbit = bits.back();
while (width > int(bits.size()))
while (width > GetSize(bits))
bits.push_back(extbit);
return RTLIL::Const(bits);
}
@ -939,13 +939,13 @@ RTLIL::Const AstNode::bitsAsUnsizedConst(int width)
RTLIL::Const AstNode::bitsAsConst(int width, bool is_signed)
{
std::vector<RTLIL::State> bits = this->bits;
if (width >= 0 && width < int(bits.size()))
if (width >= 0 && width < GetSize(bits))
bits.resize(width);
if (width >= 0 && width > int(bits.size())) {
if (width >= 0 && width > GetSize(bits)) {
RTLIL::State extbit = RTLIL::State::S0;
if ((is_signed || is_unsized) && !bits.empty())
extbit = bits.back();
while (width > int(bits.size()))
while (width > GetSize(bits))
bits.push_back(extbit);
}
return RTLIL::Const(bits);
@ -1029,7 +1029,7 @@ double AstNode::asReal(bool is_signed)
val = const_neg(val, val, false, false, val.size());
double v = 0;
for (size_t i = 0; i < val.size(); i++)
for (auto i = 0; i < val.size(); i++)
// IEEE Std 1800-2012 Par 6.12.2: Individual bits that are x or z in
// the net or the variable shall be treated as zero upon conversion.
if (val.at(i) == RTLIL::State::S1)