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Improved handling of initialized registers

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Clifford Wolf 2013-11-23 16:26:59 +01:00
parent 532091afcb
commit 1de12e1efc
1 changed files with 10 additions and 10 deletions
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20
frontends/verilog/parser.y
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@ -250,12 +250,12 @@ optional_comma:
module_arg_opt_assignment: module_arg_opt_assignment:
'=' expr { '=' expr {
if (ast_stack.back()->children.size() > 0 && ast_stack.back()->children.back()->type == AST_WIRE) { if (ast_stack.back()->children.size() > 0 && ast_stack.back()->children.back()->type == AST_WIRE) {
if (!ast_stack.back()->children.back()->is_reg) { AstNode *wire = new AstNode(AST_IDENTIFIER);
AstNode *wire = new AstNode(AST_IDENTIFIER); wire->str = ast_stack.back()->children.back()->str;
wire->str = ast_stack.back()->children.back()->str; if (ast_stack.back()->children.back()->is_reg)
ast_stack.back()->children.push_back(new AstNode(AST_INITIAL, new AstNode(AST_BLOCK, new AstNode(AST_ASSIGN_LE, wire, $2))));
else
ast_stack.back()->children.push_back(new AstNode(AST_ASSIGN, wire, $2)); ast_stack.back()->children.push_back(new AstNode(AST_ASSIGN, wire, $2));
} else
ast_stack.back()->children.back()->attributes["\\init"] = $2;
} else } else
frontend_verilog_yyerror("Syntax error."); frontend_verilog_yyerror("Syntax error.");
} | } |
@ -525,12 +525,12 @@ wire_name_list:
wire_name_and_opt_assign: wire_name_and_opt_assign:
wire_name | wire_name |
wire_name '=' expr { wire_name '=' expr {
if (!astbuf1->is_reg) { AstNode *wire = new AstNode(AST_IDENTIFIER);
AstNode *wire = new AstNode(AST_IDENTIFIER); wire->str = ast_stack.back()->children.back()->str;
wire->str = ast_stack.back()->children.back()->str; if (astbuf1->is_reg)
ast_stack.back()->children.push_back(new AstNode(AST_INITIAL, new AstNode(AST_BLOCK, new AstNode(AST_ASSIGN_LE, wire, $3))));
else
ast_stack.back()->children.push_back(new AstNode(AST_ASSIGN, wire, $3)); ast_stack.back()->children.push_back(new AstNode(AST_ASSIGN, wire, $3));
} else
ast_stack.back()->children.back()->attributes["\\init"] = $3;
}; };
wire_name: wire_name: