mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-06-06 14:13:23 +00:00
Code Activity

Write yosys version to output files

Browse source
This commit is contained in:
Clifford Wolf 2013-11-03 21:41:39 +01:00
parent eab536a203
commit 1dcb683fcb
7 changed files with 13 additions and 9 deletions
Download patch file Download diff file Expand all files Collapse all files

4
backends/verilog/verilog_backend.cc
View file

@ -803,6 +803,7 @@ void dump_module(FILE *f, std::string indent, RTLIL::Module *module)
reset_auto_counter(module);
active_module = module;
fprintf(f, "\n");
for (auto it = module->processes.begin(); it != module->processes.end(); it++)
dump_process(f, indent + " ", it->second, true);
@ -956,6 +957,7 @@ struct VerilogBackend : public Backend {
}
extra_args(f, filename, args, argidx);
fprintf(f, "/* Generated by %s */\n", yosys_version_str);
for (auto it = design->modules.begin(); it != design->modules.end(); it++) {
if (it->second->get_bool_attribute("\\placeholder") != placeholders)
continue;
@ -964,8 +966,6 @@ struct VerilogBackend : public Backend {
log_cmd_error("Can't handle partially selected module %s!\n", RTLIL::id2cstr(it->first));
continue;
}
if (it != design->modules.begin())
fprintf(f, "\n");
log("Dumping module `%s'.\n", it->first.c_str());
dump_module(f, "", it->second);
}