mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-11-04 13:29:12 +00:00
Code Activity

Add @cliffordwolf freduce testcase

Browse source
This commit is contained in:
Eddie Hung 2019-06-07 12:12:11 -07:00
parent e263bc249b
commit 1da12c5071
2 changed files with 30 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

13
tests/various/muxpack.v
View file

@ -166,3 +166,16 @@ module cliffordwolf_nonexclusive_select (
if (z) o = d; if (z) o = d;
end end
endmodule endmodule
module cliffordwolf_freduce (
input wire [1:0] s,
input wire a, b, c, d,
output reg [3:0] o
);
always @* begin
o = {4{a}};
if (s == 0) o = {3{b}};
if (s == 1) o = {2{c}};
if (s == 2) o = d;
end
endmodule

17
tests/various/muxpack.ys
View file

@ -178,3 +178,20 @@ design -import gold -as gold
design -import gate -as gate design -import gate -as gate
miter -equiv -flatten -make_assert -make_outputs gold gate miter miter -equiv -flatten -make_assert -make_outputs gold gate miter
sat -verify -prove-asserts -show-ports miter sat -verify -prove-asserts -show-ports miter
design -load read
hierarchy -top cliffordwolf_freduce
prep
design -save gold
proc; opt; freduce; opt
write_verilog -noexpr -norename
muxpack
opt
stat
select -assert-count 0 t:$mux
select -assert-count 1 t:$pmux
design -stash gate
design -import gold -as gold
design -import gate -as gate
miter -equiv -flatten -make_assert -make_outputs gold gate miter
sat -verify -prove-asserts -show-ports miter