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Add @cliffordwolf freduce testcase
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@ -178,3 +178,20 @@ design -import gold -as gold
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design -import gate -as gate
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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sat -verify -prove-asserts -show-ports miter
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design -load read
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hierarchy -top cliffordwolf_freduce
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prep
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design -save gold
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proc; opt; freduce; opt
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write_verilog -noexpr -norename
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muxpack
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opt
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stat
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select -assert-count 0 t:$mux
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select -assert-count 1 t:$pmux
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design -stash gate
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design -import gold -as gold
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design -import gate -as gate
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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sat -verify -prove-asserts -show-ports miter
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