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Add @cliffordwolf freduce testcase
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@ -166,3 +166,16 @@ module cliffordwolf_nonexclusive_select (
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if (z) o = d;
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end
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endmodule
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module cliffordwolf_freduce (
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input wire [1:0] s,
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input wire a, b, c, d,
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output reg [3:0] o
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);
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always @* begin
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o = {4{a}};
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if (s == 0) o = {3{b}};
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if (s == 1) o = {2{c}};
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if (s == 2) o = d;
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end
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endmodule
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