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Removed deprecated module->new_wire()

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This commit is contained in:
Clifford Wolf 2014-07-21 12:35:06 +02:00
parent 3cb61d03f8
commit 1d88f1cf9f
11 changed files with 47 additions and 56 deletions
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10
frontends/liberty/liberty.cc
View file

@ -227,8 +227,8 @@ static RTLIL::SigSpec parse_func_expr(RTLIL::Module *module, const char *expr)
static void create_ff(RTLIL::Module *module, LibertyAst *node) static void create_ff(RTLIL::Module *module, LibertyAst *node)
{ {
RTLIL::SigSpec iq_sig(module->new_wire(1, RTLIL::escape_id(node->args.at(0)))); RTLIL::SigSpec iq_sig(module->addWire(RTLIL::escape_id(node->args.at(0))));
RTLIL::SigSpec iqn_sig(module->new_wire(1, RTLIL::escape_id(node->args.at(1)))); RTLIL::SigSpec iqn_sig(module->addWire(RTLIL::escape_id(node->args.at(1))));
RTLIL::SigSpec clk_sig, data_sig, clear_sig, preset_sig; RTLIL::SigSpec clk_sig, data_sig, clear_sig, preset_sig;
bool clk_polarity = true, clear_polarity = true, preset_polarity = true; bool clk_polarity = true, clear_polarity = true, preset_polarity = true;
@ -309,8 +309,8 @@ static void create_ff(RTLIL::Module *module, LibertyAst *node)
static void create_latch(RTLIL::Module *module, LibertyAst *node) static void create_latch(RTLIL::Module *module, LibertyAst *node)
{ {
RTLIL::SigSpec iq_sig(module->new_wire(1, RTLIL::escape_id(node->args.at(0)))); RTLIL::SigSpec iq_sig(module->addWire(RTLIL::escape_id(node->args.at(0))));
RTLIL::SigSpec iqn_sig(module->new_wire(1, RTLIL::escape_id(node->args.at(1)))); RTLIL::SigSpec iqn_sig(module->addWire(RTLIL::escape_id(node->args.at(1))));
RTLIL::SigSpec enable_sig, data_sig, clear_sig, preset_sig; RTLIL::SigSpec enable_sig, data_sig, clear_sig, preset_sig;
bool enable_polarity = true, clear_polarity = true, preset_polarity = true; bool enable_polarity = true, clear_polarity = true, preset_polarity = true;
@ -549,7 +549,7 @@ struct LibertyFrontend : public Frontend {
} }
} }
if (!flag_lib || dir->value != "internal") if (!flag_lib || dir->value != "internal")
module->new_wire(1, RTLIL::escape_id(node->args.at(0))); module->addWire(RTLIL::escape_id(node->args.at(0)));
} }
for (auto node : cell->children) for (auto node : cell->children)

21
kernel/rtlil.cc
View file

@ -819,15 +819,6 @@ RTLIL::Module *RTLIL::Module::clone() const
return new_mod; return new_mod;
} }
RTLIL::Wire *RTLIL::Module::new_wire(int width, RTLIL::IdString name)
{
RTLIL::Wire *wire = new RTLIL::Wire;
wire->width = width;
wire->name = name;
add(wire);
return wire;
}
void RTLIL::Module::add(RTLIL::Wire *wire) void RTLIL::Module::add(RTLIL::Wire *wire)
{ {
assert(!wire->name.empty()); assert(!wire->name.empty());
@ -908,7 +899,7 @@ RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, RTLIL::IdString type)
return cell; \ return cell; \
} \ } \
RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed) { \ RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed) { \
RTLIL::SigSpec sig_y = new_wire(_y_size, NEW_ID); \ RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
add ## _func(name, sig_a, sig_y, is_signed); \ add ## _func(name, sig_a, sig_y, is_signed); \
return sig_y; \ return sig_y; \
} }
@ -941,7 +932,7 @@ DEF_METHOD(LogicNot, 1, "$logic_not")
return cell; \ return cell; \
} \ } \
RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed) { \ RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed) { \
RTLIL::SigSpec sig_y = new_wire(_y_size, NEW_ID); \ RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
add ## _func(name, sig_a, sig_b, sig_y, is_signed); \ add ## _func(name, sig_a, sig_b, sig_y, is_signed); \
return sig_y; \ return sig_y; \
} }
@ -986,7 +977,7 @@ DEF_METHOD(LogicOr, 1, "$logic_or")
return cell; \ return cell; \
} \ } \
RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s) { \ RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s) { \
RTLIL::SigSpec sig_y = new_wire(sig_a.width, NEW_ID); \ RTLIL::SigSpec sig_y = addWire(NEW_ID, sig_a.width); \
add ## _func(name, sig_a, sig_b, sig_s, sig_y); \ add ## _func(name, sig_a, sig_b, sig_s, sig_y); \
return sig_y; \ return sig_y; \
} }
@ -1006,7 +997,7 @@ DEF_METHOD(SafePmux, "$safe_pmux", 1)
return cell; \ return cell; \
} \ } \
RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig1) { \ RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig1) { \
RTLIL::SigSpec sig2 = new_wire(1, NEW_ID); \ RTLIL::SigSpec sig2 = addWire(NEW_ID); \
add ## _func(name, sig1, sig2); \ add ## _func(name, sig1, sig2); \
return sig2; \ return sig2; \
} }
@ -1022,7 +1013,7 @@ DEF_METHOD(SafePmux, "$safe_pmux", 1)
return cell; \ return cell; \
} \ } \
RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig1, RTLIL::SigSpec sig2) { \ RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig1, RTLIL::SigSpec sig2) { \
RTLIL::SigSpec sig3 = new_wire(1, NEW_ID); \ RTLIL::SigSpec sig3 = addWire(NEW_ID); \
add ## _func(name, sig1, sig2, sig3); \ add ## _func(name, sig1, sig2, sig3); \
return sig3; \ return sig3; \
} }
@ -1039,7 +1030,7 @@ DEF_METHOD(SafePmux, "$safe_pmux", 1)
return cell; \ return cell; \
} \ } \
RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig1, RTLIL::SigSpec sig2, RTLIL::SigSpec sig3) { \ RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig1, RTLIL::SigSpec sig2, RTLIL::SigSpec sig3) { \
RTLIL::SigSpec sig4 = new_wire(1, NEW_ID); \ RTLIL::SigSpec sig4 = addWire(NEW_ID); \
add ## _func(name, sig1, sig2, sig3, sig4); \ add ## _func(name, sig1, sig2, sig3, sig4); \
return sig4; \ return sig4; \
} }

10
kernel/rtlil.h
View file

@ -142,7 +142,7 @@ namespace RTLIL
RTLIL::new_id(__FILE__, __LINE__, __FUNCTION__) RTLIL::new_id(__FILE__, __LINE__, __FUNCTION__)
#define NEW_WIRE(_mod, _width) \ #define NEW_WIRE(_mod, _width) \
(_mod)->new_wire(_width, NEW_ID) (_mod)->addWire(NEW_ID, _width)
template <typename T> struct sort_by_name { template <typename T> struct sort_by_name {
bool operator()(T *a, T *b) const { bool operator()(T *a, T *b) const {
@ -287,16 +287,16 @@ struct RTLIL::Module {
virtual size_t count_id(RTLIL::IdString id); virtual size_t count_id(RTLIL::IdString id);
virtual void check(); virtual void check();
virtual void optimize(); virtual void optimize();
RTLIL::Wire *new_wire(int width, RTLIL::IdString name);
void add(RTLIL::Wire *wire);
void add(RTLIL::Cell *cell);
void remove(RTLIL::Cell *cell);
void fixup_ports(); void fixup_ports();
template<typename T> void rewrite_sigspecs(T functor); template<typename T> void rewrite_sigspecs(T functor);
void cloneInto(RTLIL::Module *new_mod) const; void cloneInto(RTLIL::Module *new_mod) const;
virtual RTLIL::Module *clone() const; virtual RTLIL::Module *clone() const;
void add(RTLIL::Wire *wire);
void add(RTLIL::Cell *cell);
void remove(RTLIL::Cell *cell);
RTLIL::Wire *addWire(RTLIL::IdString name, int width = 1); RTLIL::Wire *addWire(RTLIL::IdString name, int width = 1);
RTLIL::Cell *addCell(RTLIL::IdString name, RTLIL::IdString type); RTLIL::Cell *addCell(RTLIL::IdString name, RTLIL::IdString type);

2
passes/cmds/connect.cc
View file

@ -27,7 +27,7 @@ static void unset_drivers(RTLIL::Design *design, RTLIL::Module *module, SigMap &
{ {
CellTypes ct(design); CellTypes ct(design);
RTLIL::Wire *dummy_wire = module->new_wire(sig.width, NEW_ID); RTLIL::Wire *dummy_wire = module->addWire(NEW_ID, sig.width);
for (auto &it : module->cells) for (auto &it : module->cells)
for (auto &port : it.second->connections) for (auto &port : it.second->connections)

2
passes/cmds/delete.cc
View file

@ -30,7 +30,7 @@ struct DeleteWireWorker
sig.optimize(); sig.optimize();
for (auto &c : sig.chunks) for (auto &c : sig.chunks)
if (c.wire != NULL && delete_wires_p->count(c.wire->name)) { if (c.wire != NULL && delete_wires_p->count(c.wire->name)) {
c.wire = module->new_wire(c.width, NEW_ID); c.wire = module->addWire(NEW_ID, c.width);
c.offset = 0; c.offset = 0;
} }
} }

4
passes/cmds/splice.cc
View file

@ -77,7 +77,7 @@ struct SpliceWorker
cell->parameters["\\A_WIDTH"] = sig_a.width; cell->parameters["\\A_WIDTH"] = sig_a.width;
cell->parameters["\\Y_WIDTH"] = sig.width; cell->parameters["\\Y_WIDTH"] = sig.width;
cell->connections["\\A"] = sig_a; cell->connections["\\A"] = sig_a;
cell->connections["\\Y"] = module->new_wire(sig.width, NEW_ID); cell->connections["\\Y"] = module->addWire(NEW_ID, sig.width);
new_sig = cell->connections["\\Y"]; new_sig = cell->connections["\\Y"];
module->add(cell); module->add(cell);
} }
@ -138,7 +138,7 @@ struct SpliceWorker
cell->parameters["\\B_WIDTH"] = sig2.width; cell->parameters["\\B_WIDTH"] = sig2.width;
cell->connections["\\A"] = new_sig; cell->connections["\\A"] = new_sig;
cell->connections["\\B"] = sig2; cell->connections["\\B"] = sig2;
cell->connections["\\Y"] = module->new_wire(new_sig.width + sig2.width, NEW_ID); cell->connections["\\Y"] = module->addWire(NEW_ID, new_sig.width + sig2.width);
new_sig = cell->connections["\\Y"]; new_sig = cell->connections["\\Y"];
module->add(cell); module->add(cell);
} }

4
passes/memory/memory_share.cc
View file

@ -419,7 +419,7 @@ struct MemoryShareWorker
if (0) { if (0) {
found_overlapping_bits_i_j: found_overlapping_bits_i_j:
log(" Creating collosion-detect logic for port %d.\n", j); log(" Creating collosion-detect logic for port %d.\n", j);
RTLIL::SigSpec is_same_addr = module->new_wire(1, NEW_ID); RTLIL::SigSpec is_same_addr = module->addWire(NEW_ID);
module->addEq(NEW_ID, addr, wr_ports[j]->connections.at("\\ADDR"), is_same_addr); module->addEq(NEW_ID, addr, wr_ports[j]->connections.at("\\ADDR"), is_same_addr);
merged_en = mask_en_grouped(is_same_addr, merged_en, sigmap(wr_ports[j]->connections.at("\\EN"))); merged_en = mask_en_grouped(is_same_addr, merged_en, sigmap(wr_ports[j]->connections.at("\\EN")));
} }
@ -603,7 +603,7 @@ struct MemoryShareWorker
std::map<std::pair<RTLIL::SigBit, RTLIL::SigBit>, int> groups_en; std::map<std::pair<RTLIL::SigBit, RTLIL::SigBit>, int> groups_en;
RTLIL::SigSpec grouped_last_en, grouped_this_en, en; RTLIL::SigSpec grouped_last_en, grouped_this_en, en;
RTLIL::Wire *grouped_en = module->new_wire(0, NEW_ID); RTLIL::Wire *grouped_en = module->addWire(NEW_ID, 0);
for (int j = 0; j < int(this_en.size()); j++) { for (int j = 0; j < int(this_en.size()); j++) {
std::pair<RTLIL::SigBit, RTLIL::SigBit> key(last_en[j], this_en[j]); std::pair<RTLIL::SigBit, RTLIL::SigBit> key(last_en[j], this_en[j]);

4
passes/sat/freduce.cc
View file

@ -707,7 +707,7 @@ struct FreduceWorker
log(" Connect slave%s: %s\n", grp[i].inverted ? " using inverter" : "", log_signal(grp[i].bit)); log(" Connect slave%s: %s\n", grp[i].inverted ? " using inverter" : "", log_signal(grp[i].bit));
RTLIL::Cell *drv = drivers.at(grp[i].bit).first; RTLIL::Cell *drv = drivers.at(grp[i].bit).first;
RTLIL::Wire *dummy_wire = module->new_wire(1, NEW_ID); RTLIL::Wire *dummy_wire = module->addWire(NEW_ID);
for (auto &port : drv->connections) for (auto &port : drv->connections)
if (ct.cell_output(drv->type, port.first)) if (ct.cell_output(drv->type, port.first))
sigmap(port.second).replace(grp[i].bit, dummy_wire, &port.second); sigmap(port.second).replace(grp[i].bit, dummy_wire, &port.second);
@ -716,7 +716,7 @@ struct FreduceWorker
{ {
if (inv_sig.width == 0) if (inv_sig.width == 0)
{ {
inv_sig = module->new_wire(1, NEW_ID); inv_sig = module->addWire(NEW_ID);
RTLIL::Cell *inv_cell = new RTLIL::Cell; RTLIL::Cell *inv_cell = new RTLIL::Cell;
inv_cell->name = NEW_ID; inv_cell->name = NEW_ID;

12
passes/sat/miter.cc
View file

@ -164,7 +164,7 @@ static void create_miter_equiv(struct Pass *that, std::vector<std::string> args,
if (flag_ignore_gold_x) if (flag_ignore_gold_x)
{ {
RTLIL::SigSpec gold_x = miter_module->new_wire(w2_gold->width, NEW_ID); RTLIL::SigSpec gold_x = miter_module->addWire(NEW_ID, w2_gold->width);
for (int i = 0; i < w2_gold->width; i++) { for (int i = 0; i < w2_gold->width; i++) {
RTLIL::Cell *eqx_cell = new RTLIL::Cell; RTLIL::Cell *eqx_cell = new RTLIL::Cell;
eqx_cell->name = NEW_ID; eqx_cell->name = NEW_ID;
@ -180,8 +180,8 @@ static void create_miter_equiv(struct Pass *that, std::vector<std::string> args,
miter_module->add(eqx_cell); miter_module->add(eqx_cell);
} }
RTLIL::SigSpec gold_masked = miter_module->new_wire(w2_gold->width, NEW_ID); RTLIL::SigSpec gold_masked = miter_module->addWire(NEW_ID, w2_gold->width);
RTLIL::SigSpec gate_masked = miter_module->new_wire(w2_gate->width, NEW_ID); RTLIL::SigSpec gate_masked = miter_module->addWire(NEW_ID, w2_gate->width);
RTLIL::Cell *or_gold_cell = new RTLIL::Cell; RTLIL::Cell *or_gold_cell = new RTLIL::Cell;
or_gold_cell->name = NEW_ID; or_gold_cell->name = NEW_ID;
@ -219,7 +219,7 @@ static void create_miter_equiv(struct Pass *that, std::vector<std::string> args,
eq_cell->parameters["\\B_SIGNED"] = 0; eq_cell->parameters["\\B_SIGNED"] = 0;
eq_cell->connections["\\A"] = gold_masked; eq_cell->connections["\\A"] = gold_masked;
eq_cell->connections["\\B"] = gate_masked; eq_cell->connections["\\B"] = gate_masked;
eq_cell->connections["\\Y"] = miter_module->new_wire(1, NEW_ID); eq_cell->connections["\\Y"] = miter_module->addWire(NEW_ID);
this_condition = eq_cell->connections["\\Y"]; this_condition = eq_cell->connections["\\Y"];
miter_module->add(eq_cell); miter_module->add(eq_cell);
} }
@ -235,7 +235,7 @@ static void create_miter_equiv(struct Pass *that, std::vector<std::string> args,
eq_cell->parameters["\\B_SIGNED"] = 0; eq_cell->parameters["\\B_SIGNED"] = 0;
eq_cell->connections["\\A"] = w2_gold; eq_cell->connections["\\A"] = w2_gold;
eq_cell->connections["\\B"] = w2_gate; eq_cell->connections["\\B"] = w2_gate;
eq_cell->connections["\\Y"] = miter_module->new_wire(1, NEW_ID); eq_cell->connections["\\Y"] = miter_module->addWire(NEW_ID);
this_condition = eq_cell->connections["\\Y"]; this_condition = eq_cell->connections["\\Y"];
miter_module->add(eq_cell); miter_module->add(eq_cell);
} }
@ -261,7 +261,7 @@ static void create_miter_equiv(struct Pass *that, std::vector<std::string> args,
reduce_cell->parameters["\\Y_WIDTH"] = 1; reduce_cell->parameters["\\Y_WIDTH"] = 1;
reduce_cell->parameters["\\A_SIGNED"] = 0; reduce_cell->parameters["\\A_SIGNED"] = 0;
reduce_cell->connections["\\A"] = all_conditions; reduce_cell->connections["\\A"] = all_conditions;
reduce_cell->connections["\\Y"] = miter_module->new_wire(1, NEW_ID); reduce_cell->connections["\\Y"] = miter_module->addWire(NEW_ID);
all_conditions = reduce_cell->connections["\\Y"]; all_conditions = reduce_cell->connections["\\Y"];
miter_module->add(reduce_cell); miter_module->add(reduce_cell);
} }

26
passes/sat/share.cc
View file

@ -276,11 +276,11 @@ struct ShareWorker
int a_width = std::max(a1.width, a2.width); int a_width = std::max(a1.width, a2.width);
int y_width = std::max(y1.width, y2.width); int y_width = std::max(y1.width, y2.width);
if (a1.width != a_width) a1 = module->addPos(NEW_ID, a1, module->new_wire(a_width, NEW_ID), a_signed)->connections.at("\\Y"); if (a1.width != a_width) a1 = module->addPos(NEW_ID, a1, module->addWire(NEW_ID, a_width), a_signed)->connections.at("\\Y");
if (a2.width != a_width) a2 = module->addPos(NEW_ID, a2, module->new_wire(a_width, NEW_ID), a_signed)->connections.at("\\Y"); if (a2.width != a_width) a2 = module->addPos(NEW_ID, a2, module->addWire(NEW_ID, a_width), a_signed)->connections.at("\\Y");
RTLIL::SigSpec a = module->Mux(NEW_ID, a2, a1, act); RTLIL::SigSpec a = module->Mux(NEW_ID, a2, a1, act);
RTLIL::Wire *y = module->new_wire(y_width, NEW_ID); RTLIL::Wire *y = module->addWire(NEW_ID, y_width);
RTLIL::Cell *supercell = new RTLIL::Cell; RTLIL::Cell *supercell = new RTLIL::Cell;
supercell->name = NEW_ID; supercell->name = NEW_ID;
@ -375,24 +375,24 @@ struct ShareWorker
{ {
a_width = std::max(y_width, a_width); a_width = std::max(y_width, a_width);
if (a1.width < y1.width) a1 = module->addPos(NEW_ID, a1, module->new_wire(y1.width, NEW_ID), true)->connections.at("\\Y"); if (a1.width < y1.width) a1 = module->addPos(NEW_ID, a1, module->addWire(NEW_ID, y1.width), true)->connections.at("\\Y");
if (a2.width < y2.width) a2 = module->addPos(NEW_ID, a2, module->new_wire(y2.width, NEW_ID), true)->connections.at("\\Y"); if (a2.width < y2.width) a2 = module->addPos(NEW_ID, a2, module->addWire(NEW_ID, y2.width), true)->connections.at("\\Y");
if (a1.width != a_width) a1 = module->addPos(NEW_ID, a1, module->new_wire(a_width, NEW_ID), false)->connections.at("\\Y"); if (a1.width != a_width) a1 = module->addPos(NEW_ID, a1, module->addWire(NEW_ID, a_width), false)->connections.at("\\Y");
if (a2.width != a_width) a2 = module->addPos(NEW_ID, a2, module->new_wire(a_width, NEW_ID), false)->connections.at("\\Y"); if (a2.width != a_width) a2 = module->addPos(NEW_ID, a2, module->addWire(NEW_ID, a_width), false)->connections.at("\\Y");
} }
else else
{ {
if (a1.width != a_width) a1 = module->addPos(NEW_ID, a1, module->new_wire(a_width, NEW_ID), a_signed)->connections.at("\\Y"); if (a1.width != a_width) a1 = module->addPos(NEW_ID, a1, module->addWire(NEW_ID, a_width), a_signed)->connections.at("\\Y");
if (a2.width != a_width) a2 = module->addPos(NEW_ID, a2, module->new_wire(a_width, NEW_ID), a_signed)->connections.at("\\Y"); if (a2.width != a_width) a2 = module->addPos(NEW_ID, a2, module->addWire(NEW_ID, a_width), a_signed)->connections.at("\\Y");
} }
if (b1.width != b_width) b1 = module->addPos(NEW_ID, b1, module->new_wire(b_width, NEW_ID), b_signed)->connections.at("\\Y"); if (b1.width != b_width) b1 = module->addPos(NEW_ID, b1, module->addWire(NEW_ID, b_width), b_signed)->connections.at("\\Y");
if (b2.width != b_width) b2 = module->addPos(NEW_ID, b2, module->new_wire(b_width, NEW_ID), b_signed)->connections.at("\\Y"); if (b2.width != b_width) b2 = module->addPos(NEW_ID, b2, module->addWire(NEW_ID, b_width), b_signed)->connections.at("\\Y");
RTLIL::SigSpec a = module->Mux(NEW_ID, a2, a1, act); RTLIL::SigSpec a = module->Mux(NEW_ID, a2, a1, act);
RTLIL::SigSpec b = module->Mux(NEW_ID, b2, b1, act); RTLIL::SigSpec b = module->Mux(NEW_ID, b2, b1, act);
RTLIL::Wire *y = module->new_wire(y_width, NEW_ID); RTLIL::Wire *y = module->addWire(NEW_ID, y_width);
RTLIL::Cell *supercell = module->addCell(NEW_ID, c1->type); RTLIL::Cell *supercell = module->addCell(NEW_ID, c1->type);
supercell->parameters["\\A_SIGNED"] = a_signed; supercell->parameters["\\A_SIGNED"] = a_signed;
@ -617,7 +617,7 @@ struct ShareWorker
RTLIL::SigSpec make_cell_activation_logic(const std::set<std::pair<RTLIL::SigSpec, RTLIL::Const>> &activation_patterns) RTLIL::SigSpec make_cell_activation_logic(const std::set<std::pair<RTLIL::SigSpec, RTLIL::Const>> &activation_patterns)
{ {
RTLIL::Wire *all_cases_wire = module->new_wire(0, NEW_ID); RTLIL::Wire *all_cases_wire = module->addWire(NEW_ID, 0);
for (auto &p : activation_patterns) { for (auto &p : activation_patterns) {
all_cases_wire->width++; all_cases_wire->width++;
module->addEq(NEW_ID, p.first, p.second, RTLIL::SigSpec(all_cases_wire, 1, all_cases_wire->width - 1)); module->addEq(NEW_ID, p.first, p.second, RTLIL::SigSpec(all_cases_wire, 1, all_cases_wire->width - 1));

8
passes/techmap/simplemap.cc
View file

@ -89,7 +89,7 @@ static void simplemap_bitop(RTLIL::Module *module, RTLIL::Cell *cell)
if (cell->type == "$xnor") if (cell->type == "$xnor")
{ {
RTLIL::SigSpec sig_t = module->new_wire(width, NEW_ID); RTLIL::SigSpec sig_t = module->addWire(NEW_ID, width);
sig_t.expand(); sig_t.expand();
for (int i = 0; i < width; i++) { for (int i = 0; i < width; i++) {
@ -158,7 +158,7 @@ static void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell)
while (sig_a.width > 1) while (sig_a.width > 1)
{ {
RTLIL::SigSpec sig_t = module->new_wire(sig_a.width / 2, NEW_ID); RTLIL::SigSpec sig_t = module->addWire(NEW_ID, sig_a.width / 2);
sig_t.expand(); sig_t.expand();
for (int i = 0; i < sig_a.width; i += 2) for (int i = 0; i < sig_a.width; i += 2)
@ -182,7 +182,7 @@ static void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell)
} }
if (cell->type == "$reduce_xnor") { if (cell->type == "$reduce_xnor") {
RTLIL::SigSpec sig_t = module->new_wire(1, NEW_ID); RTLIL::SigSpec sig_t = module->addWire(NEW_ID);
RTLIL::Cell *gate = new RTLIL::Cell; RTLIL::Cell *gate = new RTLIL::Cell;
gate->name = NEW_ID; gate->name = NEW_ID;
gate->type = "$_INV_"; gate->type = "$_INV_";
@ -206,7 +206,7 @@ static void logic_reduce(RTLIL::Module *module, RTLIL::SigSpec &sig)
while (sig.width > 1) while (sig.width > 1)
{ {
RTLIL::SigSpec sig_t = module->new_wire(sig.width / 2, NEW_ID); RTLIL::SigSpec sig_t = module->addWire(NEW_ID, sig.width / 2);
sig_t.expand(); sig_t.expand();
for (int i = 0; i < sig.width; i += 2) for (int i = 0; i < sig.width; i += 2)