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https://github.com/YosysHQ/yosys
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Removed deprecated module->new_wire()
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3cb61d03f8
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1d88f1cf9f
11 changed files with 47 additions and 56 deletions
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@ -419,7 +419,7 @@ struct MemoryShareWorker
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if (0) {
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found_overlapping_bits_i_j:
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log(" Creating collosion-detect logic for port %d.\n", j);
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RTLIL::SigSpec is_same_addr = module->new_wire(1, NEW_ID);
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RTLIL::SigSpec is_same_addr = module->addWire(NEW_ID);
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module->addEq(NEW_ID, addr, wr_ports[j]->connections.at("\\ADDR"), is_same_addr);
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merged_en = mask_en_grouped(is_same_addr, merged_en, sigmap(wr_ports[j]->connections.at("\\EN")));
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}
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@ -603,7 +603,7 @@ struct MemoryShareWorker
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std::map<std::pair<RTLIL::SigBit, RTLIL::SigBit>, int> groups_en;
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RTLIL::SigSpec grouped_last_en, grouped_this_en, en;
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RTLIL::Wire *grouped_en = module->new_wire(0, NEW_ID);
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RTLIL::Wire *grouped_en = module->addWire(NEW_ID, 0);
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for (int j = 0; j < int(this_en.size()); j++) {
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std::pair<RTLIL::SigBit, RTLIL::SigBit> key(last_en[j], this_en[j]);
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