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Removed deprecated module->new_wire()

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This commit is contained in:
Clifford Wolf 2014-07-21 12:35:06 +02:00
parent 3cb61d03f8
commit 1d88f1cf9f
11 changed files with 47 additions and 56 deletions
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2
passes/cmds/connect.cc
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@ -27,7 +27,7 @@ static void unset_drivers(RTLIL::Design *design, RTLIL::Module *module, SigMap &
{
CellTypes ct(design);
RTLIL::Wire *dummy_wire = module->new_wire(sig.width, NEW_ID);
RTLIL::Wire *dummy_wire = module->addWire(NEW_ID, sig.width);
for (auto &it : module->cells)
for (auto &port : it.second->connections)

2
passes/cmds/delete.cc
View file

@ -30,7 +30,7 @@ struct DeleteWireWorker
sig.optimize();
for (auto &c : sig.chunks)
if (c.wire != NULL && delete_wires_p->count(c.wire->name)) {
c.wire = module->new_wire(c.width, NEW_ID);
c.wire = module->addWire(NEW_ID, c.width);
c.offset = 0;
}
}

4
passes/cmds/splice.cc
View file

@ -77,7 +77,7 @@ struct SpliceWorker
cell->parameters["\\A_WIDTH"] = sig_a.width;
cell->parameters["\\Y_WIDTH"] = sig.width;
cell->connections["\\A"] = sig_a;
cell->connections["\\Y"] = module->new_wire(sig.width, NEW_ID);
cell->connections["\\Y"] = module->addWire(NEW_ID, sig.width);
new_sig = cell->connections["\\Y"];
module->add(cell);
}
@ -138,7 +138,7 @@ struct SpliceWorker
cell->parameters["\\B_WIDTH"] = sig2.width;
cell->connections["\\A"] = new_sig;
cell->connections["\\B"] = sig2;
cell->connections["\\Y"] = module->new_wire(new_sig.width + sig2.width, NEW_ID);
cell->connections["\\Y"] = module->addWire(NEW_ID, new_sig.width + sig2.width);
new_sig = cell->connections["\\Y"];
module->add(cell);
}