mirror of
https://github.com/YosysHQ/yosys
synced 2026-05-22 01:49:45 +00:00
Merge pull request #5882 from YosysHQ/std_cpp20
Bump required standard to C++20
This commit is contained in:
commit
1d87cefd80
13 changed files with 42 additions and 32 deletions
|
|
@ -100,7 +100,7 @@ struct EstimateSta {
|
|||
cell, cell->type.unescape());
|
||||
continue;
|
||||
}
|
||||
if (ff.sig_clk != clk)
|
||||
if (!clk || ff.sig_clk.as_bit() != *clk)
|
||||
continue;
|
||||
launch.append(ff.sig_q);
|
||||
sample.append(ff.sig_d);
|
||||
|
|
@ -144,12 +144,12 @@ struct EstimateSta {
|
|||
log_error("Unsupported async memory port '%s'\n", rd.cell);
|
||||
continue;
|
||||
}
|
||||
if (sigmap(rd.clk) != clk)
|
||||
if (!clk || sigmap(rd.clk).as_bit() != *clk)
|
||||
continue;
|
||||
add_seq(rd.cell, rd.data, {rd.addr, rd.srst, rd.en});
|
||||
}
|
||||
for (auto &wr : mem.wr_ports) {
|
||||
if (sigmap(wr.clk) != clk)
|
||||
if (!clk || sigmap(wr.clk).as_bit() != *clk)
|
||||
continue;
|
||||
add_seq(wr.cell, {}, {wr.en, wr.addr, wr.data});
|
||||
}
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue