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Added support for "keep" attributes on wires

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This commit is contained in:
Clifford Wolf 2013-11-05 15:52:29 +01:00
parent 27fec4e77c
commit 1d34fd7608
2 changed files with 8 additions and 3 deletions
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6
README
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@ -254,9 +254,9 @@ Verilog Attributes and non-standard features
passes to identify input and output ports of cells. The verilog backend passes to identify input and output ports of cells. The verilog backend
also does not output placeholder modules on default. also does not output placeholder modules on default.
- The "keep" attribute on cells is used to mark cells that should never be - The "keep" attribute on cells and wires is used to mark objects that should
removed by the optimizer. This is used for example for cells that have never be removed by the optimizer. This is used for example for cells that
hidden connections that are not part of the netlist, such as IO pads. have hidden connections that are not part of the netlist, such as IO pads.
- In addition to the (* ... *) attribute syntax, yosys supports - In addition to the (* ... *) attribute syntax, yosys supports
the non-standard {* ... *} attribute syntax to set default attributes the non-standard {* ... *} attribute syntax to set default attributes

5
passes/opt/opt_clean.cc
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@ -190,6 +190,11 @@ static void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool
if (!wire->port_input) if (!wire->port_input)
used_signals_nodrivers.add(sig); used_signals_nodrivers.add(sig);
} }
if (wire->get_bool_attribute("\\keep")) {
RTLIL::SigSpec sig = RTLIL::SigSpec(wire);
assign_map.apply(sig);
used_signals.add(sig);
}
} }
std::vector<RTLIL::Wire*> del_wires; std::vector<RTLIL::Wire*> del_wires;