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https://github.com/YosysHQ/yosys
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Add a DSP_MINWIDTH macro, and soft-logic for {A_WIDTH,B_WIDTH} <= 1 too
This commit is contained in:
Eddie Hung
parent
9ad11ea2cc
commit
1d14cec7fd
1 changed files with 68 additions and 28 deletions
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@ -28,27 +28,11 @@ module \$mul (A, B, Y);
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output [Y_WIDTH-1:0] Y;
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generate
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if (A_SIGNED != B_SIGNED)
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if (A_SIGNED != B_SIGNED || A_WIDTH <= 1 || B_WIDTH <= 1)
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wire _TECHMAP_FAIL_ = 1;
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`ifdef DSP_SIGNEDONLY
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else if (!A_SIGNED) begin
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wire [1:0] dummy;
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\$mul #(
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.A_SIGNED(1),
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.B_SIGNED(1),
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.A_WIDTH(A_WIDTH + 1),
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.B_WIDTH(B_WIDTH + 1),
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.Y_WIDTH(Y_WIDTH + 2)
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) _TECHMAP_REPLACE_ (
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.A({1'b0, A}),
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.B({1'b0, B}),
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.Y({dummy, Y})
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);
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end
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`endif
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// NB: A_SIGNED == B_SIGNED == 0 from here
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else if (A_WIDTH >= B_WIDTH)
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\$__mul_gen #(
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\$__mul #(
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.A_SIGNED(A_SIGNED),
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.B_SIGNED(B_SIGNED),
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.A_WIDTH(A_WIDTH),
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@ -60,7 +44,7 @@ module \$mul (A, B, Y);
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.Y(Y)
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);
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else
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\$__mul_gen #(
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\$__mul #(
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.A_SIGNED(B_SIGNED),
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.B_SIGNED(A_SIGNED),
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.A_WIDTH(B_WIDTH),
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@ -74,7 +58,7 @@ module \$mul (A, B, Y);
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endgenerate
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endmodule
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module \$__mul_gen (A, B, Y);
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module \$__mul (A, B, Y);
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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parameter A_WIDTH = 1;
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@ -95,7 +79,13 @@ module \$__mul_gen (A, B, Y);
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genvar i;
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generate
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if (A_WIDTH > `DSP_A_MAXWIDTH) begin
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if (A_WIDTH <= 1 || B_WIDTH <= 1)
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wire _TECHMAP_FAIL_ = 1;
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`ifdef DSP_MINWIDTH
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else if (A_WIDTH+B_WIDTH < `DSP_MINWIDTH || Y_WIDTH < `DSP_MINWIDTH)
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wire _TECHMAP_FAIL_ = 1;
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`endif
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else if (A_WIDTH > `DSP_A_MAXWIDTH) begin
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localparam n = (A_WIDTH+`DSP_A_MAXWIDTH-sign_headroom-1) / (`DSP_A_MAXWIDTH-sign_headroom);
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localparam partial_Y_WIDTH = `MIN(Y_WIDTH, B_WIDTH+`DSP_A_MAXWIDTH);
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if (A_SIGNED && B_SIGNED) begin
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@ -107,7 +97,7 @@ module \$__mul_gen (A, B, Y);
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wire [Y_WIDTH-1:0] partial_sum [n-1:0];
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end
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\$__mul_gen #(
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\$__mul #(
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.A_SIGNED(sign_headroom),
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.B_SIGNED(B_SIGNED),
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.A_WIDTH(`DSP_A_MAXWIDTH),
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@ -121,7 +111,7 @@ module \$__mul_gen (A, B, Y);
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assign partial_sum[0] = partial[0];
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for (i = 1; i < n-1; i=i+1) begin:slice
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\$__mul_gen #(
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\$__mul #(
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.A_SIGNED(sign_headroom),
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.B_SIGNED(B_SIGNED),
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.A_WIDTH(`DSP_A_MAXWIDTH),
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@ -135,7 +125,7 @@ module \$__mul_gen (A, B, Y);
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assign partial_sum[i] = (partial[i] << i*(`DSP_A_MAXWIDTH-sign_headroom)) + partial_sum[i-1];
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end
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\$__mul_gen #(
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\$__mul #(
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.A_SIGNED(A_SIGNED),
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.B_SIGNED(B_SIGNED),
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.A_WIDTH(A_WIDTH-(n-1)*(`DSP_A_MAXWIDTH-sign_headroom)),
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@ -161,7 +151,7 @@ module \$__mul_gen (A, B, Y);
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wire [Y_WIDTH-1:0] partial_sum [n-1:0];
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end
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\$__mul_gen #(
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\$__mul #(
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.A_SIGNED(A_SIGNED),
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.B_SIGNED(sign_headroom),
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.A_WIDTH(A_WIDTH),
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@ -175,7 +165,7 @@ module \$__mul_gen (A, B, Y);
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assign partial_sum[0] = partial[0];
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for (i = 1; i < n-1; i=i+1) begin:slice
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\$__mul_gen #(
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\$__mul #(
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.A_SIGNED(A_SIGNED),
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.B_SIGNED(sign_headroom),
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.A_WIDTH(A_WIDTH),
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@ -189,7 +179,7 @@ module \$__mul_gen (A, B, Y);
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assign partial_sum[i] = (partial[i] << i*(`DSP_B_MAXWIDTH-sign_headroom)) + partial_sum[i-1];
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end
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\$__mul_gen #(
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\$__mul #(
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.A_SIGNED(A_SIGNED),
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.B_SIGNED(B_SIGNED),
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.A_WIDTH(A_WIDTH),
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@ -218,7 +208,7 @@ module \$__mul_gen (A, B, Y);
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.B_SIGNED(B_SIGNED),
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.A_WIDTH(`DSP_A_MAXWIDTH),
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.B_WIDTH(`DSP_B_MAXWIDTH),
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.Y_WIDTH(`DSP_A_MAXWIDTH+`DSP_B_MAXWIDTH),
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.Y_WIDTH(`MIN(Y_WIDTH,`DSP_A_MAXWIDTH+`DSP_B_MAXWIDTH)),
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) _TECHMAP_REPLACE_ (
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.A(Aext),
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.B(Bext),
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@ -228,4 +218,54 @@ module \$__mul_gen (A, B, Y);
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endgenerate
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endmodule
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(* techmap_celltype = "$__mul" *)
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module _90_internal_mul_to_external (A, B, Y);
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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parameter A_WIDTH = 1;
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parameter B_WIDTH = 1;
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parameter Y_WIDTH = 1;
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input [A_WIDTH-1:0] A;
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input [B_WIDTH-1:0] B;
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output [Y_WIDTH-1:0] Y;
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generate
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if (A_SIGNED && !B_SIGNED)
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\$mul #(
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.A_SIGNED(A_SIGNED),
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.B_SIGNED(1),
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.A_WIDTH(A_WIDTH),
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.B_WIDTH(B_WIDTH+1),
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.Y_WIDTH(Y_WIDTH)
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) _TECHMAP_REPLACE_ (
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.A(A),
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.B({1'b0, B}),
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.Y(Y)
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);
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else if (!A_SIGNED && B_SIGNED)
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\$mul #(
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.A_SIGNED(1),
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.B_SIGNED(B_SIGNED),
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.A_WIDTH(A_WIDTH+1),
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.B_WIDTH(B_WIDTH),
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.Y_WIDTH(Y_WIDTH)
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) _TECHMAP_REPLACE_ (
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.A({1'b0, A}),
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.B(B),
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.Y(Y)
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);
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else
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\$mul #(
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.A_SIGNED(A_SIGNED),
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.B_SIGNED(B_SIGNED),
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.A_WIDTH(A_WIDTH),
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.B_WIDTH(B_WIDTH),
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.Y_WIDTH(Y_WIDTH)
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) _TECHMAP_REPLACE_ (
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.A(A),
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.B(B),
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.Y(Y)
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);
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endgenerate
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endmodule
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