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Fix OPMODE for PCIN->PCOUT cascades in xc6s, check B[01]REG too

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This commit is contained in:
Eddie Hung 2019-12-23 14:40:59 -08:00
parent 75acaff6f5
commit 1d0ac659ad
1 changed files with 18 additions and 8 deletions
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26
passes/pmgen/xilinx_dsp_cascade.pmg
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@ -99,14 +99,21 @@ finally
add_siguser(cascade, dsp); add_siguser(cascade, dsp);
SigSpec opmode = port(dsp_pcin, \OPMODE, Const(0, 7)); SigSpec opmode = port(dsp_pcin, \OPMODE, Const(0, 7));
if (P == 17) if (dsp->type.in(\DSP48A, \DSP48A1)) {
opmode[6] = State::S1; log_assert(P == 0);
else if (P == 0) opmode[3] = State::S0;
opmode[6] = State::S0; opmode[2] = State::S1;
else log_abort(); }
else if (dsp->type.in(\DSP48E1)) {
if (P == 17)
opmode[6] = State::S1;
else if (P == 0)
opmode[6] = State::S0;
else log_abort();
opmode[5] = State::S0; opmode[5] = State::S0;
opmode[4] = State::S1; opmode[4] = State::S1;
}
dsp_pcin->setPort(\OPMODE, opmode); dsp_pcin->setPort(\OPMODE, opmode);
log_debug("PCOUT -> PCIN cascade for %s -> %s\n", log_id(dsp), log_id(dsp_pcin)); log_debug("PCOUT -> PCIN cascade for %s -> %s\n", log_id(dsp), log_id(dsp_pcin));
@ -307,8 +314,11 @@ code argQ clock BREG
goto reject_BREG; goto reject_BREG;
if (dffcemux && port(dffcemux, \S) != port(prev, CEB, State::S0)) if (dffcemux && port(dffcemux, \S) != port(prev, CEB, State::S0))
goto reject_BREG; goto reject_BREG;
if (dffD == unextend(port(prev, \B))) if (dffD == unextend(port(prev, \B))) {
if (next->type.in(\DSP48A, \DSP48A1) && param(prev, \B0REG, 0) != 0)
goto reject_BREG;
BREG = 1; BREG = 1;
}
} }
} }
} }