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https://github.com/YosysHQ/yosys
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symfpu: Dynamic rounding mode
This commit is contained in:
Krystine Sherwin
parent
0c8b0f0868
commit
1cd3fd5090
3 changed files with 140 additions and 83 deletions
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@ -79,6 +79,7 @@ using sbv = rtlil_traits::sbv;
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using symfpu::ite;
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using uf = symfpu::unpackedFloat<rtlil_traits>;
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using uf_flagged = symfpu::floatWithStatusFlags<rtlil_traits>;
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using uf_flagged_ite = symfpu::ite<prop, uf_flagged>;
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PRIVATE_NAMESPACE_END
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@ -411,16 +412,18 @@ struct SymFpuPass : public Pass {
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);
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auto rm_option = content_root->open_option("-rm <RM>");
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rm_option->paragraph("rounding mode to generate, must be one of the below; default=RNE");
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rm_option->paragraph("rounding mode to generate, must be one of the below; default=DYN");
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rm_option->codeblock(
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"<RM> | description\n"
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"-----+----------------------\n"
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"RNE | round ties to even\n"
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"RNA | round ties to away\n"
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"RTP | round toward positive\n"
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"RTN | round toward negative\n"
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"RTZ | round toward zero\n"
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"<RM> | rm | description\n"
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"-----+--------+----------------------\n"
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"RNE | 00001 | round ties to even\n"
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"RNA | 00010 | round ties to away\n"
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"RTP | 00100 | round toward positive\n"
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"RTN | 01000 | round toward negative\n"
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"RTZ | 10000 | round toward zero\n"
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"DYN | xxxxx | round based on 'rm' input signal\n"
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);
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rm_option->paragraph("Note: when not using DYN mode, the 'rm' input is ignored.");
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return true;
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}
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@ -428,7 +431,7 @@ struct SymFpuPass : public Pass {
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{
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//TODO: fix multiple calls to symfpu in single Yosys instance
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int eb = 8, sb = 24;
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string op = "mul", rounding = "RNE";
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string op = "mul", rounding = "DYN";
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int inputs = 2;
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log_header(design, "Executing SYMFPU pass.\n");
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@ -470,14 +473,16 @@ struct SymFpuPass : public Pass {
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rm rounding_mode;
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if (rounding.compare("RNE") == 0)
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rounding_mode = rtlil_traits::RNE();
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else if (rounding.compare("RNA") == 0)
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else if (rounding.compare("RNA") == 0)
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rounding_mode = rtlil_traits::RNA();
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else if (rounding.compare("RTP") == 0)
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else if (rounding.compare("RTP") == 0)
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rounding_mode = rtlil_traits::RTP();
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else if (rounding.compare("RTN") == 0)
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else if (rounding.compare("RTN") == 0)
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rounding_mode = rtlil_traits::RTN();
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else if (rounding.compare("RTZ") == 0)
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else if (rounding.compare("RTZ") == 0)
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rounding_mode = rtlil_traits::RTZ();
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else if (rounding.compare("DYN") == 0)
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rounding_mode = {};
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else
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log_cmd_error("Unknown rounding mode '%s'. Call help sympfpu for available rounding modes.\n", rounding);
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@ -495,12 +500,38 @@ struct SymFpuPass : public Pass {
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uf b = symfpu::unpack<rtlil_traits>(format, b_bv);
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uf c = symfpu::unpack<rtlil_traits>(format, c_bv);
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auto rm_wire = symfpu_mod->addWire(ID(rm), 5);
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rm_wire->port_input = true;
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SigSpec rm_sig(rm_wire);
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prop rm_RNE(rm_sig[0]);
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prop rm_RNA(rm_sig[1]);
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prop rm_RTP(rm_sig[2]);
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prop rm_RTN(rm_sig[3]);
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prop rm_RTZ(rm_sig[4]);
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// signaling NaN inputs raise NV
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prop signals_invalid((a.getNaN() && is_sNaN(a_bv, sb))
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|| (b.getNaN() && is_sNaN(b_bv, sb) && inputs >= 2)
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|| (c.getNaN() && is_sNaN(c_bv, sb) && inputs >= 3)
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);
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auto make_op = [&op, &format, &a, &b, &c](rm rounding_mode) {
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if (op.compare("add") == 0)
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return symfpu::add_flagged(format, rounding_mode, a, b, prop(true));
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else if (op.compare("sub") == 0)
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return symfpu::add_flagged(format, rounding_mode, a, b, prop(false));
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else if (op.compare("mul") == 0)
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return symfpu::multiply_flagged(format, rounding_mode, a, b);
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else if (op.compare("div") == 0)
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return symfpu::divide_flagged(format, rounding_mode, a, b);
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else if (op.compare("sqrt") == 0)
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return symfpu::sqrt_flagged(format, rounding_mode, a);
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else if (op.compare("muladd") == 0)
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return symfpu::fma_flagged(format, rounding_mode, a, b, c);
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else
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log_abort();
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};
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// calling this more than once will fail
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auto output_fpu = [&signals_invalid, &format](const uf_flagged &o_flagged) {
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output_prop(ID(NV), o_flagged.nv || signals_invalid);
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@ -512,20 +543,24 @@ struct SymFpuPass : public Pass {
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output_ubv(ID(o), symfpu::pack<rtlil_traits>(format, o_flagged.val));
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};
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if (op.compare("add") == 0)
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output_fpu(symfpu::add_flagged(format, rounding_mode, a, b, prop(true)));
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else if (op.compare("sub") == 0)
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output_fpu(symfpu::add_flagged(format, rounding_mode, a, b, prop(false)));
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else if (op.compare("mul") == 0)
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output_fpu(symfpu::multiply_flagged(format, rounding_mode, a, b));
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else if (op.compare("div") == 0)
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output_fpu(symfpu::divide_flagged(format, rounding_mode, a, b));
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else if (op.compare("sqrt") == 0)
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output_fpu(symfpu::sqrt_flagged(format, rounding_mode, a));
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else if (op.compare("muladd") == 0)
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output_fpu(symfpu::fma_flagged(format, rounding_mode, a, b, c));
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else
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log_abort();
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if (rounding.compare("DYN") != 0)
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output_fpu(make_op(rounding_mode));
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else {
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auto out_RNE = make_op(rtlil_traits::RNE());
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auto out_RNA = make_op(rtlil_traits::RNA());
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auto out_RTP = make_op(rtlil_traits::RTP());
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auto out_RTN = make_op(rtlil_traits::RTN());
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auto out_RTZ = make_op(rtlil_traits::RTZ());
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output_fpu(
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uf_flagged_ite::iteOp(rm_RNE, out_RNE,
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uf_flagged_ite::iteOp(rm_RNA, out_RNA,
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uf_flagged_ite::iteOp(rm_RTP, out_RTP,
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uf_flagged_ite::iteOp(rm_RTN, out_RTN,
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uf_flagged_ite::iteOp(rm_RTZ, out_RTZ,
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uf_flagged::makeNaN(format, prop(true)))))))
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);
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}
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symfpu_mod->fixup_ports();
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}
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@ -1,5 +1,6 @@
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module edges();
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(* anyseq *) reg [31:0] a, b, c;
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(* anyseq *) reg [4:0] rm;
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reg [31:0] o;
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reg NV, DZ, OF, UF, NX;
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symfpu mod (.*);
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@ -166,15 +167,16 @@ module edges();
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assign rounded_000 = '0;
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`endif
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`ifdef RTP
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wire c_muladd_turning = c_sig == '0;
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`elsif RTN
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wire c_muladd_turning = c_sig < 23'h400000;
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`elsif RTZ
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wire c_muladd_turning = c_sig == '0;
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`else // RNA || RNE (default)
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wire c_muladd_turning = c_sig <= 23'h200000;
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`endif
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wire rm_RNE = rm[0] == 1'b1;
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wire rm_RNA = rm[1:0] == 2'b10;
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wire rm_RTP = rm[2:0] == 3'b100;
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wire rm_RTN = rm[3:0] == 4'b1000;
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wire rm_RTZ = rm[4:0] == 5'b10000;
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wire c_muladd_turning = rm_RNE || rm_RNA ? c_sig <= 23'h200000 :
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rm_RTP ? c_sig == '0 :
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rm_RTN ? c_sig < 23'h400000 :
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c_sig == '0;
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always @* begin
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if (a_nan || b_nan || c_nan) begin
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@ -212,29 +214,6 @@ module edges();
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// underflow is always inexact
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assert (NX);
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`ifdef RNE
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if (OF) // output = +-inf
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assert (o_inf);
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`elsif RNA
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if (OF) // output = +-inf
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assert (o_inf);
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`elsif RTP
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if (OF) // output = +inf or -max
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assert (o == pos_inf || o == neg_max);
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if (o == neg_inf)
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assert (!OF);
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`elsif RTN
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if (OF) // output = +max or -inf
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assert (o == pos_max || o == neg_inf);
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if (o == pos_inf)
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assert (!OF);
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`elsif RTZ
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if (OF) // output = +-max
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assert (o == pos_max || o == neg_max);
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if (o_inf) // cannot overflow to infinity
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assert (!OF);
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`endif
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if (UF)
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// output = subnormal or zero
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assert (o_subnorm || o_zero);
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@ -304,32 +283,73 @@ module edges();
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`endif
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`ifdef RNE
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if (round_p_001) assert (o_unsigned == rounded_000);
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if (round_p_011) assert (o_unsigned == rounded_100);
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if (round_n_001) assert (o_unsigned == rounded_000);
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if (round_n_011) assert (o_unsigned == rounded_100);
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assume (rm_RNE);
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`elsif RNA
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if (round_p_001) assert (o_unsigned == rounded_010);
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if (round_p_011) assert (o_unsigned == rounded_100);
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if (round_n_001) assert (o_unsigned == rounded_010);
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if (round_n_011) assert (o_unsigned == rounded_100);
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assume (rm_RNA);
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`elsif RTP
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if (round_p_001) assert (o_unsigned == rounded_010);
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if (round_p_011) assert (o_unsigned == rounded_100);
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if (round_n_001) assert (o_unsigned == rounded_000);
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if (round_n_011) assert (o_unsigned == rounded_010);
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assume (rm_RTP);
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`elsif RTN
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if (round_p_001) assert (o_unsigned == rounded_000);
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if (round_p_011) assert (o_unsigned == rounded_010);
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if (round_n_001) assert (o_unsigned == rounded_010);
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if (round_n_011) assert (o_unsigned == rounded_100);
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assume (rm_RTN);
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`elsif RTZ
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if (round_p_001) assert (o_unsigned == rounded_000);
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if (round_p_011) assert (o_unsigned == rounded_010);
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if (round_n_001) assert (o_unsigned == rounded_000);
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if (round_n_011) assert (o_unsigned == rounded_010);
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assume (rm_RTZ);
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`else
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assume ($onehot(rm));
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`endif
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if (OF)
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// rounding mode determines if overflow value is inf or max
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casez (rm)
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5'bzzzz1 /* RNE */: assert (o_inf);
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5'bzzz10 /* RNA */: assert (o_inf);
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5'bzz100 /* RTP */: assert (o == pos_inf || o == neg_max);
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5'bz1000 /* RTN */: assert (o == pos_max || o == neg_inf);
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5'b10000 /* RTZ */: assert (o == pos_max || o == neg_max);
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endcase
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// RTx modes cannot overflow to the far infinity
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if (rm_RTP && o == neg_inf)
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assert (!OF);
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if (rm_RTN && o == pos_inf)
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assert (!OF);
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// RTZ cannot overflow to either
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if (rm_RTZ && o_inf)
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assert (!OF);
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// test rounding
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if (round_p_001)
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casez (rm)
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5'bzzzz1 /* RNE */: assert (o_unsigned == rounded_000);
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5'bzzz10 /* RNA */: assert (o_unsigned == rounded_010);
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5'bzz100 /* RTP */: assert (o_unsigned == rounded_010);
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5'bz1000 /* RTN */: assert (o_unsigned == rounded_000);
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5'b10000 /* RTZ */: assert (o_unsigned == rounded_000);
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endcase
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if (round_p_011)
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casez (rm)
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5'bzzzz1 /* RNE */: assert (o_unsigned == rounded_100);
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5'bzzz10 /* RNA */: assert (o_unsigned == rounded_100);
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5'bzz100 /* RTP */: assert (o_unsigned == rounded_100);
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5'bz1000 /* RTN */: assert (o_unsigned == rounded_010);
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5'b10000 /* RTZ */: assert (o_unsigned == rounded_010);
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endcase
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if (round_n_001)
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casez (rm)
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5'bzzzz1 /* RNE */: assert (o_unsigned == rounded_000);
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5'bzzz10 /* RNA */: assert (o_unsigned == rounded_010);
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5'bzz100 /* RTP */: assert (o_unsigned == rounded_000);
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5'bz1000 /* RTN */: assert (o_unsigned == rounded_010);
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5'b10000 /* RTZ */: assert (o_unsigned == rounded_000);
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endcase
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if (round_n_011)
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casez (rm)
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5'bzzzz1 /* RNE */: assert (o_unsigned == rounded_100);
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5'bzzz10 /* RNA */: assert (o_unsigned == rounded_100);
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5'bzz100 /* RTP */: assert (o_unsigned == rounded_010);
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5'bz1000 /* RTN */: assert (o_unsigned == rounded_100);
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5'b10000 /* RTZ */: assert (o_unsigned == rounded_010);
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endcase
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`ifdef ADDS
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if (use_lhs) begin
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// inf - inf
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@ -10,9 +10,11 @@ prove_rm() {
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rm=$2
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defs=$3
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ys_file=${op}_${rm}_edges.ys
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echo "symfpu -op $op -rm $rm" > $ys_file
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if [[ $rm != "DYN" ]] then
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echo "sat -prove-asserts -verify" >> $ys_file
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fi
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echo """\
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symfpu -op $op -rm $rm
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sat -prove-asserts -verify
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chformal -remove
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opt
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@ -20,13 +22,13 @@ read_verilog -sv -formal $defs -D${rm} edges.sv
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chformal -lower
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prep -top edges -flatten
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sat -set-assumes -prove-asserts -verify
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""" > $ys_file
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""" >> $ys_file
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}
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prove_op() {
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op=$1
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defs=$2
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rms="RNE RNA RTP RTN RTZ"
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rms="RNE RNA RTP RTN RTZ DYN"
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for rm in $rms; do
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prove_rm $op $rm "$defs"
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done
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